724 asic jobs at 112 companies in California
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
3d
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ASIC Design Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree in a relevant technical field, ASIC, FPGA, or SoC design experience, digital design and architecture knowledge, industry-standard design tools, and Python, Tcl, Perl, or similar scripting experience.
Python, Tcl, Perl, RTL, FPGA, SoC, ASIC, IP, STA
2w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
3mo
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Analog ASIC Architect
Austin or San Francisco
HybridFull Time
10+ YOEExperience in analog and mixed-signal ASIC architecture; BS and at least 10 years experience.
MATLAB, Python
2w
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
1w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with test planning, coverage, assertions, randomization, and simulation debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
2mo
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Senior ASIC Design Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOE8+ years RTL build/ASIC design, Verilog/SystemVerilog, ASIC flow knowledge, Bachelors/Masters in EE/CE.
Verilog, SystemVerilog, Digital Design, ASIC flow, timing analysis, RTL, ECO, Synthesis, Post-Silicon Debug
1mo
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ASIC Technology Librarian
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS or equivalent experience, 4 years managing vendor engagements and library delivery schedules in an ASIC design environment, LEC and library validation tool experience, familiarity with foundry PDKs, and scripting in Tcl or Python.
Formality, Conformal, Siemens Solido Crosscheck, Fractal Crossfire, TSMC, Synopsys, PDKs, Tcl, Python
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ASIC Implementation Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
10+ YOETop-level floorplanning and chip integration expertise, experience resolving physical design DRC/LVS/EMIR issues, scripting in Python/Tcl/Perl, familiarity with EDA tools, 10+ years of relevant ASIC physical design experience; must work onsite in San Jose.
Python, Tcl, Perl, EDA tools, DRC, LVS, EMIR
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
1mo
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
2mo
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ASIC Architect
Sunnyvale, California, United States
OnsiteFull Time
10+ YOEMasters or PhD in Electrical/Computer Engineering; 10+ years performance analysis and modeling experience across GPUs/CPUs/accelerators; strong computer architecture background; ability to build performance models in Python.
Python
1w
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
1mo
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
1mo
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Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
5+ YOEM.S. or Ph.D. in EE/CE, 5+ years ASIC front-end RTL ownership, SystemVerilog/HLS proficiency, UVM/DPI/C++ familiarity, and Python scripting for EDA flows.
FPGA, ASIC, SystemVerilog, Verilog, High Level Synthesis (HLS), UVM, DPI, C++, Python, GitHub Copilot, Claude, ChatGPT
1w
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Senior ASIC Design Verification Engineer
San Jose, California, United States
$168k-$245k/yr OnsiteFull Time
7+ YOEBachelor's degree plus 7+ years, master's plus 4+ years, or PhD plus 1 year in ASIC experience; requires SystemVerilog, UVM, ASIC verification processes, debugging, and block-to-full-chip verification.
SystemVerilog, UVM, Linux, C, C++, Python, Perl, PCIe, AXI
4d
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
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