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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
3w
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
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ASIC Design Engineer
California or United States
OnsiteFull Time
10+ YOEBachelor's degree with 10+ years of experience in ASIC design and hardware architecture.
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
2mo
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ASIC Design Engineer
United States
RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
0+ YOEBS or MS in Electrical Engineering or Computer Engineering; 0–2 years ASIC digital design; SystemVerilog/Verilog RTL; digital design fundamentals; cross-functional collaboration.
SystemVerilog, Verilog, RTL, Synthesis, Timing
2mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
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ASIC Design Engineer
Irvine or Andover
$127k-$203k/yr OnsiteFull Time
7+ YOEBachelors with 12+ years, or Masters with 10+ years, or PhD with 7+ years in ASIC design/implementation; expertise in synthesis, floorplanning, place-and-route, timing, power, SI, and DFT.
Synthesis, Place and Route, Clock Methodology, Power Planning, Timing Analysis, Signal Integrity, DFT, EDA Tools
1w
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
1w
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
2mo
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ASIC Design Engineer lll
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
4+ YOEBachelor's in electrical engineering; 4+ years in ASIC/SoC design; strong Verilog/SystemVerilog; experience with EDA tools; good communication; Perl/Python a plus; AI tool experience a plus.
Verilog, SystemVerilog, EDA tools, Perl, Python
1mo
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Experienced Engineer - ASIC Design
Bangalore or Chennai or India or Sweden or United States
OnsiteFull Time
5+ YOEBachelors in electrical/computer engineering, 5+ years ASIC IP design experience, proficiency in SystemVerilog, RTL sign-off (SpyGlass), scripting (TCL, Python), AMBA (AXI, CHI), Cadence/Synopsys tool suites, and strong English communication.
SystemVerilog, SpyGlass, TCL, Python, AMBA, AXI, CHI, SystemVerilog Assertions, Cadence, Synopsys, Jenkins, Simscope, Jira, UPF
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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
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ASIC/SoC Design Engineer
San Jose or United States
$146k-$250k/yr OnsiteFull Time
Experience in ASIC/SoC design, RTL/verification, Verilog/SystemVerilog, timing constraints, PD integration, DFT, and cross-domain collaboration.
Verilog, SystemVerilog, SystemVerilog Assertions, SDC timing constraints, ASIC CAD tools, AMBA AXI/AXI-S/APB, UPF, Perl, Python, Makefile
2mo
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ASIC Physical Design Manager
Colorado Springs, Colorado, United States
$151k-$253k/yr OnsiteFull Time
7+ YOE5+ MgmtB.S. or M.S. in Electrical/Computer Engineering; 7+ years digital ASIC physical design; 5+ years project/program management; tapeout experience.
Place and Route, Timing analysis, DFT, Signoff tools, Physical design methodologies
1mo
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Senior Engineer - ASIC Design (786532)
Bengaluru or Chennai or Sweden or United States
OnsiteFull Time
10+ YOEBachelor's in electrical/computer engineering, 10+ years ASIC IP design, SystemVerilog, SpyGlass, synthesis/timing knowledge, TCL/Python scripting, AMBA (AXI/CHI), SVA; Cadence and Synopsys experience preferred.
SystemVerilog, SpyGlass, TCL, Python, AMBA, AXI, CHI, Cadence, Synopsys, MATLAB, UPF, Jenkins, Simscope, Jira
2mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
2mo
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ASIC Digital Design Engineer-17369
Boxborough or Markham or Mississauga or Ottawa
$138k-$208k/yr OnsiteFull Time
Experienced ASIC digital designer/verifier with Verilog, Perl, Tcl, and Python skills; knowledge of RTL design/verification, static timing analysis, synthesis, simulation, and debugging; HBM/DDR protocol experience preferred.
Verilog, Perl, Tcl, Python
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Senior ASIC Package Design Engineer
Los Angeles or United States
$180k-$260k/yr RemoteFull Time
5+ YOEBachelor's in engineering, 5+ years ASIC package design experience (FC-BGA), expertise in substrate technologies, SI/PI and thermal management, experience with OSATs and package qualification.
SIWave, HFSS, ADS
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ASIC Design Verification Engineer
Santa Clara, California, United States
$106k-$172k/yr OnsiteFull Time
3+ YOEBS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
SystemVerilog, UVM, Python, C++, Perl, UNIX Shell
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ASIC Design Verification Engineer
United States
$200k-$350k/yr RemoteFull Time
8+ YOE8+ years ASIC verification; degree in EE/CE; SystemVerilog UVM; testbenches and coverage-driven verification; experience with EDA tools; scripting (Python/Perl/TCL).
SystemVerilog, UVM, Simulation tools, Cadence tools, Synopsys tools, Mentor Graphics tools, Python, Perl, TCL
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