121 asic design jobs at 30 companies in Austin, TX
2mo
Save
Mark Applied
Hide
ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
2d
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
2w
Save
Mark Applied
Hide
ASIC Digital Design Engineer Lead
Austin, Texas, United States
OnsiteFull Time
Senior engineering leader with strong ASIC/digital design background, supplier engagement, cross-functional communication, and schedule-driven delivery.
1mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer - Agentic AI
Santa Clara or Durham or Austin
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent, 8+ years experience, expertise in micro-architecture and RTL (Verilog), ASIC design flow, Python proficiency, and experience with LLM fine-tuning, RAG pipelines and vector databases.
Verilog, Python, large language models, RAG pipelines, vector databases
1mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models
2d
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debug; scripting; and a bachelor's or master's degree in electrical or computer engineering preferred.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF
1mo
Save
Mark Applied
Hide
ASIC Engineer, Physical Design
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
3mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
2d
Save
Mark Applied
Hide
ASIC Design Verification Engineer (784248)
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debugging; scripting with TCL, Python, or Perl; and a bachelor's or master's degree in engineering or equivalent experience.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, AMBA APB, AXI, ACE-Lite, CHI
3mo
Save
Mark Applied
Hide
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
3+ YOEBachelor's degree (or equivalent), 3+ years ASIC design/architecture experience, proficiency in SystemVerilog, RTL design, synthesis and timing-aware implementation, strong analytical and collaboration skills.
SystemVerilog
1mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
2mo
Save
Mark Applied
Hide
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer (Santa Clara, CA)
Santa Clara or Austin
$127k-$190k/yr OnsiteFull Time
3+ YOE3+ years DV experience using UVM/assertion-based verification; experience verifying SoC/subsystems, caches, DDR, memory VIPs, DDR PHY, formal verification, PASIM, C++ and Python exposure; bachelor's/master's/PhD in science or engineering.
UVM, SystemVerilog, C++, Python, PASIM, UPF
4d
Save
Mark Applied
Hide
AI/ML driven ASIC Design and Implementation Automation Engineer
Austin, Texas, United States
OnsiteFull Time
1+ YOEBS or MS in a relevant discipline, Python/C++ programming, 1–2 years of AI/ML experience, optimization algorithms, Unix/Linux, Git, software debugging, and strong analytical and communication skills.
Python, C++, Unix, Linux, Git, BitBucket, SystemVerilog, Verilog, VHDL, DesignSync, Make, Splunk, Jenkins, LSF, CI/CD, SDC, UPF, LLMs, CNN, RNN, GraphNN, GenAI, Reinforcement Learning, Graph Neural Networks
1mo
Save
Mark Applied
Hide
Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
2mo
Save
Mark Applied
Hide
Design Engineer I - Modem Design
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Degree in electrical/computer engineering or related; experience with RTL design using Verilog/SystemVerilog, digital design and verification, MATLAB/Python for automation, and familiarity with FPGA/ASIC flows and wireless/DSP concepts.
Verilog, SystemVerilog, MATLAB, Python, Questa
2mo
Save
Mark Applied
Hide
ASIC Verification Technical-Lead Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOE3+ Mgmt10+ years in digital design verification, 3+ years leading verification teams, expertise with SystemVerilog/UVM, VLSI verification flows, completed multiple full block/system verification cycles, strong leadership and debugging skills.
SystemVerilog, UVM, eRM, OVM, Python, Perl
1w
Save
Mark Applied
Hide
DFT Design Engineer
Austin or San Jose
OnsiteFull Time
3+ YOE3-12 years SoC/ASIC digital design experience with focus on DFT, scan insertion, compression scan, MBIST, ATPG, EMR not required. US citizenship preferred.
Cadence, Verilog, ATPG, MBIST, JTAG 1149.1, JTAG 1149.6, IEEE1500, IEEE1687
2mo
Save
Mark Applied
Hide
Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
Explore Jobs
Expand Your Job Search
Top Cities Near Austin for Asic Design
- Asic Design jobs in Round Rock, TX
- Asic Design jobs in New Braunfels, TX
- Asic Design jobs in Cedar Park, TX
- Asic Design jobs in Georgetown, TX
- Asic Design jobs in San Marcos, TX
- Asic Design jobs in Pflugerville, TX
- Asic Design jobs in Leander, TX
- Asic Design jobs in Kyle, TX
- Asic Design jobs in Hutto, TX
- Asic Design jobs in Taylor, TX
- Asic Design jobs in Lakeway, TX
- Asic Design jobs in Buda, TX
- Asic Design jobs in Lockhart, TX
- Asic Design jobs in Elgin, TX
- Asic Design jobs in Bastrop, TX
- Asic Design jobs in Manor, TX
- Asic Design jobs in Lago Vista, TX
- Asic Design jobs in Bee Cave, TX
- Asic Design jobs in Marble Falls, TX
- Asic Design jobs in Burnet, TX