550 asic design jobs at 90 companies in California
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ASIC Design Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree in a relevant technical field, ASIC, FPGA, or SoC design experience, digital design and architecture knowledge, industry-standard design tools, and Python, Tcl, Perl, or similar scripting experience.
Python, Tcl, Perl, RTL, FPGA, SoC, ASIC, IP, STA
1w
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ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
3mo
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Senior ASIC Design Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOE8+ years RTL build/ASIC design, Verilog/SystemVerilog, ASIC flow knowledge, Bachelors/Masters in EE/CE.
Verilog, SystemVerilog, Digital Design, ASIC flow, timing analysis, RTL, ECO, Synthesis, Post-Silicon Debug
3w
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ASIC Design Engineer
California or Texas or Massachusetts
HybridFull Time
Hands-on experience with multiple advanced-node tapeouts and ownership of ASIC design for blocks; understanding of PPA improvement and design methodology for rapid iterations. Large-die, AI-chip, and multi-chiplet experience preferred.
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
1mo
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
2w
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Senior ASIC Design Engineer
San Jose, California, United States
$168k-$245k/yr OnsiteFull Time
7+ YOEBachelor’s degree in Electrical or Computer Engineering plus 7+ years, master’s plus 4+ years, or PhD plus 1+ year of ASIC design experience; Verilog/SystemVerilog experience required.
Verilog, SystemVerilog, scripting
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Senior ASIC Design Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
8+ YOEBachelor's degree or equivalent experience in electrical, computer, or software engineering; 8+ years' experience; micro-architecture and Verilog RTL development; ASIC design flow, digital systems, and VLSI expertise.
Verilog, C++, C, Python, Perl
5d
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ASIC Design Engineer 2
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Bachelor's degree in Electrical Engineering required; master's preferred. Requires digital logic coursework, Verilog/SystemVerilog coding through coursework or projects, analytical skills, and familiarity with ASIC design; Perl/Python knowledge is a plus.
SystemVerilog, Verilog, Perl, Python, EDA tools, SVA
2mo
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Lead ASIC Design Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE12+ years ASIC/SoC digital design experience, BS/MS in EE/CE, expert SystemVerilog/Verilog, front-end EDA tool fluency, proven tape-out history, US work authorization, strong communication and mentoring skills.
SystemVerilog, Verilog, SDC, CDC, Design Compiler, Genus, PrimeTime, Tempus, Lint, SpyGlass, JasperGold CDC, Synopsys, Cadence, Python, Tcl, Perl
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
2d
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ASIC Design Engineer — Pixel IP
Sunnyvale or California
OnsiteFull Time
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of relevant industry experience; expertise in RTL digital logic design, Verilog or SystemVerilog, and ASIC/FPGA methodologies.
RTL, Verilog, SystemVerilog, AMBA, AXI, AHB, APB, Python, Perl, TCL, FPGA
2w
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
1w
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ASIC Design Engineer – DSP / Analog / SerDes
Ottawa or Irvine or San Jose
OnsiteFull Time
5+ YOEBachelor’s or higher degree in electrical or computer engineering; 5+ years of digital ASIC design experience; proficiency in Verilog/SystemVerilog; experience with ASIC flows, EDA tools, DSP, SerDes, verification, and automation.
Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM, EDA, RTL, Clock Domain Crossing (CDC), FEC, CDR, PLL, CTLE, DFE, ADC, DAC
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ASIC Engineer, Design for Test
Sunnyvale, California, United States
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent practical experience, 6+ years in DFT engineering for complex ASIC or SoC designs, DFT EDA tools, fault coverage, silicon bring-up, manufacturing test, and Tcl, Python, or Perl scripting.
Tessent, Synopsys DFT Compiler, TetraMAX, Tcl, Python, Perl, IEEE 1500, IEEE 1687 (IJTAG), IEEE 1149.1, ATE, DRC, LVS, ASIC, SoC, ATPG, MBIST, LBIST, SerDes
1mo
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ASIC Design Engineer
San Jose, California, United States
OnsiteFull Time
BS/MS/PhD in Electrical/Computer Engineering; proficiency in RTL design using Verilog/SystemVerilog, logic and micro-architecture, familiarity with AMBA/PCIe/NAND/DDR, scripting (Python/Perl/TCL), and Linux command-line.
Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl, TCL, Linux
3mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
4mo
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Manager, ASIC Design Engineering (Starshield Satellite Engineering)
Hawthorne, California, United States
$190k-$245k/yr OnsiteFull Time
5+ YOE2+ MgmtLead ASIC/FPGA design team; RTL/Verilog; 5+ years RTL/FPGA/ASIC; 2+ years management; Bachelor's in engineering.
Verilog, SystemVerilog, HDL simulators, VCS, Questa, IES, Spyglass, Xilinx Vivado, Altera Quartus II, Python, TCL, EDA tools
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