94 asic design verification engineer jobs at 31 companies in San Jose, CA
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ASIC Design Verification Engineer
San Jose, California, United States
$155k-$223k/yr OnsiteFull Time
5+ YOEBachelor's degree plus 5+ years, master's plus 3+ years, or PhD plus 1+ year in a related field. Requires SystemVerilog, UVM, ASIC verification, debugging, and block-to-chip verification experience.
SystemVerilog, UVM, Linux, C, C++, Python, Perl, PCIe, AXI
2mo
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years SystemVerilog/UVM or C/C++ verification, IP/SoC verification experience, EDA and scripting (Python, TCL, Perl, Shell), experience with assertions, formal or emulation.
SystemVerilog, UVM, OVM, C, C++, Python, TCL, Perl, Shell
1mo
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ASIC Design Verification Engineer, TPU Cloud Compute
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS or equivalent, 4+ years design verification experience, proficiency with SystemVerilog/Verilog and UVM, experience across verification lifecycle and SoC projects, familiarity with ASIC interfaces and memory architecture.
SystemVerilog, Verilog, Universal Verification Methodology (UVM)
2mo
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ASIC Design Verification Engineer
Mountain View, California, United States
$175k-$215k/yr HybridFull Time
3+ YOE3+ years experience with UVM/SystemVerilog, constrained-random, functional coverage, SVA; strong RTL debug skills; Python proficiency; excellent communication and analytical abilities.
UVM, SystemVerilog, SVA, Python, C, C++, UPF, PCIe Gen 5, PCIe Gen 6, DDR5, Ethernet, LLMs
3w
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ASIC Verification Engineer
Santa Clara, California, United States
$116k-$219k/yr HybridFull Time
3+ YOE3+ years verification experience, BS/MS in EE/ECE or equivalent, expertise in logic design and verification flows (UVM, formal), strong System Verilog, C++, and scripting skills.
System Verilog, UVM, C++, Perl, Python, Formal Verification
1mo
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Sr. ASIC Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$175k-$280k/yr OnsiteFull Time
5+ YOEBachelor’s in EE/CE,5+ years design verification experience, proficiency with UVM/OVM/VMM, strong OOP and scripting (Python), RTL verification, ability to work extended hours.
UVM, OVM, VMM, Python
1mo
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
4d
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
7h
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Principal Design Verification Engineer
San Jose, California, United States
$180k-$255k/yr OnsiteFull Time
7+ YOEBachelor's or master's degree in EE, CS, or CE and 7+ years of ASIC design verification experience. Requires SystemVerilog, SVA, UVM/OVM/VMM, Python, C/C++, complex ASIC verification, coverage closure, and technical leadership.
SystemVerilog, SVA, UVM, OVM, VMM, Python, C, C++, PCIe, Ethernet, HBM, DDR, Claude, FPGA
2w
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Design Verification Engineer
Santa Clara, California, United States
HybridFull Time
Experience in ASIC/SoC design verification, developing directed and random tests, debugging RTL, collaborating with RTL/firmware teams; familiarity with Verilog/SystemVerilog, UVM, C/C++ and scripting languages preferred.
Verilog, System Verilog, UVM, C, C++, Python, Perl, TCL
3mo
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ASIC Design Engineer - Pixel IP DMA
Cupertino or Sunnyvale
OnsiteFull Time
0+ YOEBachelor's degree plus 0 years experience; front-end ASIC RTL design; multimedia IP/SoC exposure; collaboration across architecture, design, verification; DMA engines and interconnects experience.
RTL design, Synthesis, AMBA (AXI/AHB/APB), Linting, Formal verification, Performance analysis
3mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
4w
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AIML enhanced Design/Verification Methodology Engineer
Sunnyvale, California, United States
$81k-$164k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CE/CS,1+ years ASIC/SoC design-verification experience, familiarity with AIML methodologies, strong SystemVerilog and UVM skills, experience with industry simulators and verification closure.
AIML, SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium, Veloce, Python, Perl, TCL, UPF, CPF
4w
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AIML enhanced Design/Verification Methodology Engineer
Sunnyvale, California, United States
$81k-$164k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CE/CS required,1+ years ASIC/SoC design or verification experience, proficiency in SystemVerilog/UVM, familiarity with AIML methodologies, simulation and verification tool experience, strong communication skills.
AIML, Generative-AI, SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium, Veloce, Python, Perl, TCL, UPF, CPF
2w
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Staff Design Verification Engineer – High Performance CPU Core
Austin or Santa Clara
OnsiteFull Time
7+ YOE7+ years ASIC/CPU/SoC design verification experience, strong SystemVerilog and UVM skills, CPU microarchitecture knowledge, BS in EE/CE/CS, strong debug and verification strategy abilities.
SystemVerilog, UVM, Python, C, C++
4w
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification, emulation platforms, SoC verification strategy and leadership.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, Artificial Intelligence, Machine Learning, PCIe, CXL, HBM3, NVLink
4w
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Director, Design Verification
Santa Clara, California, United States
$195k-$292k/yr OnsiteFull Time
10+ YOE10+ years SOC/design verification experience; strong verification methodology, testbench development, scripting (Perl, Python, Tcl, UNIX Shell); ASIC/SoC tape-out experience; excellent communication and cross-functional leadership.
Perl, Python, Tcl, UNIX Shell
3mo
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Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
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