22 asic engineer jobs at 4 companies in Auburn, CA
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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Staff/Principal Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEB.S. in EE/CS or equivalent, 6+ years verification experience, RTL debugging, scoreboarding, code coverage analysis, test-plan development; System-Verilog/UVM expertise preferred; familiarity with C and emulation advantageous.
System-Verilog, UVM, C, Claude-Code, RTL
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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Senior Technologist, Hardware Development Engineering -
Roseville, California, United States
$177k-$235k/yr OnsiteFull Time
Expert-level hardware engineer with hands-on board and ASIC integration experience, high-speed interface and SI/PI expertise, lab bring-up and root-cause debug, and cross-functional technical leadership.
Cadence, Altium, Mentor, IBIS, AMI, S-parameters, SPICE, Oscilloscope, BERT, Network Analyzer, Spectrum Analyzer, JTAG, PRBS, IBERT
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