839 asic engineer jobs at 125 companies in California
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
4d
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ASIC Engineer
San Jose, California, United States
$155k-$223k/yr OnsiteFull Time
5+ YOEBachelor's degree and 5+ years, master's degree and 3+ years, or PhD with 0 years in ASIC design; requires Verilog/SystemVerilog, DFT/EDA tools, debugging, and scripting experience.
Python, Perl, Tcl, Shell, LSF, Verilog, SystemVerilog, Synopsys Design Constraints (SDC)
3w
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ASIC Design Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree in a relevant technical field, ASIC, FPGA, or SoC design experience, digital design and architecture knowledge, industry-standard design tools, and Python, Tcl, Perl, or similar scripting experience.
Python, Tcl, Perl, RTL, FPGA, SoC, ASIC, IP, STA
1w
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ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2w
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ASIC Production Engineer
San Jose, California, United States
$122k-$160k/yr OnsiteFull Time
8+ YOEMaster’s degree in electronics, electrical engineering, or related discipline; preferably 8+ years in ASIC production, test, and assembly; digital and analog electronics, statistical analysis, Six Sigma, Python or C++, and strong problem-solving skills.
Python, C++, Six Sigma, MIL-STD
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Senior ASIC Verification Engineer (PCIe/CXL)
San Jose or San Diego or Austin or Longmont
$146k-$250k/yr HybridFull Time
Expertise in ASIC verification, Verilog, SystemVerilog, UVM testbenches, and Python or Perl scripting; experience with PCIe, CXL, NVMe, or Ethernet; bachelor's or master's degree in computer or electrical engineering.
FPGA, ASIC, UVM, Verilog, SystemVerilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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Senior ASIC Verification Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent in electrical engineering, computer engineering, or computer science; 5+ years of ASIC verification experience; UVM, C/C++, scripting, SoC, coverage, and debugging expertise.
UVM, C/C++, Python, Perl, TCL, SVA, Perforce, Makefiles, AXI, APB, DMA, QSPI, UART, I2C, Ethernet, ARM, LLM
3w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with test planning, coverage, assertions, randomization, and simulation debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
3d
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ASIC Verification Engineer
Irvine, California, United States
OnsiteFull Time
3+ YOEMSEE/CS for new graduates or BSEE/CS with 3+ years of ASIC design or verification experience; requires HDL proficiency, logic design, architecture, networking, and scripting skills.
SystemVerilog, UVM, Verilog, VHDL, C, C++, Python, Perl, TCL
1w
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Senior ASIC Verification Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent experience in electrical, computer engineering, or computer science; 5+ years in ASIC verification; UVM, C/C++, scripting, SoC, coverage, and formal verification expertise.
UVM, C/C++, SVA, Python, Perl, TCL, Makefiles, Perforce, AXI/APB
3w
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ASIC Design Engineer
California or Texas or Massachusetts
HybridFull Time
Hands-on experience with multiple advanced-node tapeouts and ownership of ASIC design for blocks; understanding of PPA improvement and design methodology for rapid iterations. Large-die, AI-chip, and multi-chiplet experience preferred.
1w
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Senior ASIC Verification Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's degree or equivalent experience in electrical, computer, or software engineering; 5+ years of ASIC verification experience; UVM, C/C++, scripting, coverage, formal checks, and SoC-level verification expertise.
UVM, C/C++, Python, Perl, TCL, SVA, Perforce, Makefiles, AI tools
3w
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
2w
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
1w
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ASIC Design Engineer – DSP / Analog / SerDes
Ottawa or Irvine or San Jose
OnsiteFull Time
5+ YOEBachelor’s or higher degree in electrical or computer engineering; 5+ years of digital ASIC design experience; proficiency in Verilog/SystemVerilog; experience with ASIC flows, EDA tools, DSP, SerDes, verification, and automation.
Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM, EDA, RTL, Clock Domain Crossing (CDC), FEC, CDR, PLL, CTLE, DFE, ADC, DAC
2d
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ASIC Design Engineer — Pixel IP
Sunnyvale or California
OnsiteFull Time
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of relevant industry experience; expertise in RTL digital logic design, Verilog or SystemVerilog, and ASIC/FPGA methodologies.
RTL, Verilog, SystemVerilog, AMBA, AXI, AHB, APB, Python, Perl, TCL, FPGA
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