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FPGA Engineer Intern (Summer 2027 - Chicago)
Chicago, Illinois, United States
$80k/yr OnsiteInternship
Student in computer/electrical engineering or related field on track to graduate Dec 2027–Jun 2028; hands-on FPGA/ASIC digital design experience; VHDL/Verilog/System Verilog experience; strong engineering instincts and collaboration skills.
FPGA, ASIC, VHDL, Verilog, System Verilog
2d
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FPGA Engineer Intern (Summer 2027 - Austin)
Austin or Chicago
OnsiteInternship
Student in Computer/Electrical Engineering (BS/MS/PhD) graduating Dec 2027–Jun 2028; hands-on FPGA/ASIC digital design experience; VHDL/Verilog/System Verilog experience; strong engineering instincts and teamwork skills.
FPGAs, ASICs, VHDL, Verilog, System Verilog
2d
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Graduate FPGA Engineer (2027 Start - Chicago)
Chicago, Illinois, United States
$200k/yr OnsiteFull Time
Currently pursuing BS/MS/PhD in Computer or Electrical Engineering, on track to graduate Dec 2026–Jun 2027; hands-on FPGA/ASIC digital design experience; proficiency in VHDL/Verilog/System Verilog; strong engineering instincts and teamwork skills.
VHDL, Verilog, System Verilog
2mo
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Senior FPGA Engineer
Chicago, Illinois, United States
$145k/yr OnsiteFull Time
10+ YOESenior FPGA/ASIC design with Verilog/SystemVerilog; RTL; timing; verification; Python/Bash; strong collaboration; BS in CS/EE; MS a plus.
Verilog, SystemVerilog, VHDL, Python, Bash, RTL
1mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
1mo
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FPGA Engineer
Chicago, Illinois, United States
$120k-$170k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC experience, expert SystemVerilog and FPGA design, SoC and high-speed transceiver knowledge, simulation/verification skills, degree in EE/CE, strong analytical and collaboration skills.
SystemVerilog
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
1mo
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Principal/ Sr. Principal FPGA Design Engineer
Rolling Meadows, Illinois, United States
$120k-$224k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Top Secret/SCI; Bachelor's in EE/CE (or similar); 5+ years FPGA/ASIC design (8+ for senior); VHDL/Verilog, HLS (Xilinx Vivado HLS/Mentor Catapult), Python/C/C++, DSP and FPGA toolchain experience.
VHDL, Verilog, Xilinx Vivado HLS, Mentor Catapult HLS, C++, Python, C, Electronic Design Automation (EDA) Tools, Mentor Graphics ModelSim, QuestaSim, Synplify, Xilinx ISE, Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder, SystemVerilog, Universal Verification Methodology (UVM), MATLAB, Simulink, AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet, GIT, SVN, ClearCase, DOORS, Jira, Rally, ClearQuest, Signal Generators, Logic Analyzers, Digital Oscilloscopes
1mo
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Principal/ Sr. Principal FPGA Design Engineer
Rolling Meadows, Illinois, United States
$120k-$224k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Top Secret/SCI clearance; B.S. in EE/CE or similar plus 5+ years FPGA/ASIC design (8+ for senior level). Requires VHDL/Verilog, HLS (Vivado/Mentor Catapult), timing closure, DSP knowledge, Python/C/C++, testbench and FPGA design flow experience.
VHDL, Verilog, Xilinx Vivado HLS, Mentor Catapult HLS, C++, Python, C, MATLAB, Simulink, Mentor Graphics ModelSim, QuestaSim, Synplify, Xilinx ISE, Xilinx Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder, SystemVerilog, Universal Verification Methodology (UVM), GIT, SVN, ClearCase, DOORS, Jira, Rally, ClearQuest, AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet
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Research Engineer, Pre-Training
Chicago or London or New York City
$300k-$350k/yr OnsiteFull Time
Expert in large-scale distributed training, HPC or distributed systems, GPUs/TPUs and high-performance networking, Python and PyTorch/JAX; published research and advanced degree (MS/PhD) or equivalent industry experience.
GPUs, TPUs, NVLink, InfiniBand, Kubernetes, Slurm, Python, PyTorch, JAX, CUDA, Triton, Pallas, CuTe, XLA, FPGA, ASIC