15 asic engineer jobs at 7 companies in Bourne, MA
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Mixed Signal ASIC Engineer
Boston, Massachusetts, United States
OnsiteFull Time
5+ YOEPhD in electrical engineering or equivalent industry experience; 5+ years designing analog/mixed-signal ICs; strong ADC/DAC, amplifiers; tape-out experience; Cadence or Synopsys tools; end-to-end IC development.
Cadence, Synopsys
2mo
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FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
4w
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Principal FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
Proven RTL proficiency (Verilog or VHDL), real-world FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD/Lattice/Intel), embedded C/C++ experience, and exposure to ASIC verification workflows.
Verilog, VHDL, C, C++, Xilinx, AMD, Lattice, Intel/Altera
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
2w
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Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
1mo
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FPGA Design Engineer II
Needham, Massachusetts, United States
$129k-$166k/yr OnsiteFull Time
3+ YOEBS/MS in related field, 3+ years FPGA/ASIC digital logic design, proficiency in SystemVerilog or VHDL, experience with simulation/debug tools (VCS, Verdi), Linux, strong debugging and communication skills.
SystemVerilog, VHDL, VCS, Verdi, Linux, C, Python, Perl, PCIe, Ethernet, DDR
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
2w
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Sr. Design for Test (DFT) Engineer
Mountain View or Boston or Toronto
$164k-$185k/yr HybridFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT experience for advanced ASICs,pre- and post-silicon validation,Python/TCL scripting,Verilog,knowledge of scan/ATPG/MBIST/JTAG and commercial EDA DFT tools.
Python, TCL, Verilog, ATPG, MBIST, JTAG, ATE
2w
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Sr. Design for Test (DFT) Engineer
Boston or Mountain View or Toronto
$154k-$218k/yr HybridFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT experience for advanced ASICs,pre-/post-silicon validation,Python/TCL scripting,Verilog,ATPG/MBIST/JTAG expertise,commercial EDA DFT tool experience.
Python, TCL, Verilog, ATPG, MBIST, JTAG, Boundary Scan, ATE
1mo
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
1mo
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience; strong SystemVerilog and Python skills; deep understanding of cache-coherent interconnects, protocols (CHI/ACE/CXL/AXI), test plans, assertions, and coverage models; BS/MS in EE/CE/CS required.
SystemVerilog, Python
2mo
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Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
2mo
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Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
1mo
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Principal Heterogenues AI Accelerator Lead
Boston or San Jose
$200k-$275k/yr OnsiteFull Time
10+ YOEPhD or Master’s in computer/electrical engineering, 10+ years in analog/digital AI accelerator or embedded systems, ASIC/RTL/SystemVerilog expertise, SystemC modeling, UVM, C, and technical leadership experience.
Synopsys Platform Architect, SystemVerilog, SystemC, UVM, C, RTL
3w
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Director of Business Development
Boston or United States
RemoteFull Time
8+ YOE8+ years selling engineering or semiconductor services, Bachelor's degree or equivalent, ability to sell turnkey design and onshore staffing, technical competency in electronic design, familiarity with defense/secure verticals preferred.
AMD, Altera, Intel, Xilinx, FPGA, ASIC
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