19 rtl engineer jobs at 9 companies in Bourne, MA
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
1mo
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$206k-$251k/yr OnsiteFull Time
Expertise in interconnect, cache/coherency and RTL generator design; strong software engineering and hardware RTL skills; BS/MS in EE/CE/CS or equivalent experience.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Bluespec, Git, Github, Jira, Confluence, TileLink, RISC-V, AXI, AHB, APB, CHI
2mo
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FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
3mo
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FPGA Engineer (MA, Boston)
Boston, Massachusetts, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, HDL, C/C++, Python; VHDL/Verilog; hardware security; IP core development; FPGA toolchains; Xilinx/Intel devices; simulation and verification; system integration; embedded software testing; cryptography; cocotb/pyuvm.
RTL, VHDL, Verilog, Python, C, C++, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, Xilinx, FPGA verification tools, cocotb, pyuvm
1mo
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
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Power Management Design Engineer
Santa Clara or Cambridge or Austin or Boston
$159k-$194k/yr OnsiteFull Time
3+ YOERequires 3+ years in CPU/SoC clocking, reset, and power-management design; RTL proficiency; CPU or SoC development through tapeout; and a BS/MS in a technical discipline or equivalent experience.
Verilog, SystemVerilog, VHDL, SpyGlass, AMBA, AXI, AHB, APB, Scala, Chisel, Bluespec, RISC-V, Git, GitHub, Jira, Confluence, Lint, CDC, RDC, MBIST, DFT, DVFS, RTL
2mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1w
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Senior FPGA Engineer
Norwood, Massachusetts, United States
OnsiteFull Time
7+ YOE7+ years FPGA/RTL experience, proficiency with RTL design and simulation, Verilog/SystemVerilog, Modelsim/VCS/Xcelium; BS/MS/PhD required; experience with AMD/Altera toolchains preferred.
Modelsim, VCS, Xcelium, Python, C/C++, Verilog, System Verilog
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$140k-$171k/yr OnsiteFull Time
Requires BS/MS in EE, CE, CS, or related discipline or equivalent experience; RTL design, cache and interconnect knowledge, bus protocols, software engineering, and verification skills.
RISC-V, TileLink, Chisel, Scala, FIRRTL, Verilog, SystemVerilog, VHDL, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
1mo
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
4w
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Principal FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
Proven RTL proficiency (Verilog or VHDL), real-world FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD/Lattice/Intel), embedded C/C++ experience, and exposure to ASIC verification workflows.
Verilog, VHDL, C, C++, Xilinx, AMD, Lattice, Intel/Altera
2mo
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Principal Audio/DSP Systems Engineer
Boston, Massachusetts, United States
$200k-$275k/yr OnsiteFull Time
10+ YOEPhD in Electrical Engineering or related field; 10+ years in audio/signal processing; deployment on DSP/NPU; fixed-point, PTQ/QAT; C/Python/MATLAB; RTL verification; embedded AI inference.
C, Python, MATLAB, TensorFlow/TFLite, PyTorch/ONNX, DSP, RTL verification, SIMD, NPU, Fixed-point programming, Model quantization, Beamforming
1mo
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
1mo
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Principal Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$231k-$283k/yr OnsiteFull Time
Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence
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Power Management Design Engineer
Santa Clara or Austin or Boston
$140k-$171k/yr OnsiteFull Time
3+ YOERequires 3+ years in CPU/SoC clocking, reset, and power-management logic; RTL design with Verilog, SystemVerilog, or VHDL; CPU/SoC development through tapeout; and a BS/MS in a technical discipline or equivalent.
Verilog, SystemVerilog, VHDL, SpyGlass, AMBA, AXI, AHB, APB, Scala, Chisel, Bluespec, RISC-V, Git, GitHub, Jira, Confluence
5d
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Power Management Design Engineer
Santa Clara or Cambridge or Austin or Boston
$206k-$251k/yr OnsiteFull Time
3+ YOERequires 3+ years designing CPU/SoC clocking, reset, and power-management logic; RTL proficiency in Verilog, SystemVerilog, or VHDL; CPU/SoC development through tapeout; and a technical BS/MS or equivalent experience.
Verilog, SystemVerilog, VHDL, Spyglass, Scala, Chisel, Bluespec, Git, GitHub, Jira, Confluence, AMBA, AXI, AHB, APB, RISC-V, TileLink, DFT, MBIST, DVFS, Lint, CDC, RDC
3mo
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Software Engineer II (Full Stack, Platform)
Boston, Massachusetts, United States
$125k-$175k/yr OnsiteFull Time
3+ YOE2–4 years experience; JS/TypeScript, React, Node.js; REST APIs; i18n, RTL; UI components; CI/CD; collaboration.
JavaScript, TypeScript, React, Node.js, REST APIs, PostgreSQL, MySQL, CircleCI, GitHub Actions, Figma, CSS, WCAG, Storybook, i18n, RTL, BiDi
1mo
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Principal Heterogenues AI Accelerator Lead
Boston or San Jose
$200k-$275k/yr OnsiteFull Time
10+ YOEPhD or Master’s in computer/electrical engineering, 10+ years in analog/digital AI accelerator or embedded systems, ASIC/RTL/SystemVerilog expertise, SystemC modeling, UVM, C, and technical leadership experience.
Synopsys Platform Architect, SystemVerilog, SystemC, UVM, C, RTL
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Hardware Designer
Boston or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelor's in Electrical/Computer Engineering, strong high-speed circuit and PCB design skills, experience with DDR/PCIe/SerDes, test and bring-up, and mentoring experience.
LTSpice, OrCAD Capture CIS, Cadence Allegro, Verilog, RTL, HLS, optical test sets, signal analyzers, GHz+ oscilloscopes, VNAs
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