29 asic engineer jobs at 14 companies in Castle Rock, CO
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
1d
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2w
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Analog ASIC Design Engineer
Boulder or Beaverton
$149k-$277k/yr OnsiteFull Time
5+ YOEBSEE/MSEE and 5+ years analog/mixed-signal IC design experience, proficiency with ASIC design tools, layout and RF analysis, strong communication, willingness to travel domestically, must be a U.S. Person.
Ansys HFSS, Cadence EMX
2w
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Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
1mo
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Senior ASIC Digital / DSP Design Engineer
Colorado Springs, Colorado, United States
$142k-$236k/yr OnsiteFull Time
10+ YOEBS/MS in Electrical or Computer Engineering, 10+ years experience in digital and mixed-signal ASIC and DSP design/verification; strong EE and DSP fundamentals; leadership and communication skills.
Cadence, Mentor
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
1mo
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Senior ASIC Digital / DSP Design Engineer
Colorado Springs, Colorado, United States
$142k-$236k/yr OnsiteFull Time
10+ YOEBS/MS in EE/CE,10+ years experience in digital/DSP/ASIC design and verification,RTL and DSP algorithm development,experience with ASIC/FPGA flows and verification,strong math and communication skills,US-person required.
Cadence, Mentor
1mo
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
23h
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Senior Digital Signal Processing (DSP) Engineer
Englewood, Colorado, United States
$130k-$185k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years of experience required. Requires DSP, RF communications, MATLAB, C/C++, Verilog or VHDL, FPGA or ASIC implementation, communication skills, and US citizenship.
MATLAB, C, C++, Verilog, VHDL, FPGA, ASIC
2w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1w
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Principal Engineer - Digital Design
Colorado Springs, Colorado, United States
$75k-$232k/yr OnsiteFull Time
10+ YOEBS/MS in Electrical or Computer Engineering with 10+ years ASIC/digital design experience; expertise in synthesis, STA, DFT, FPGA/ASIC bring-up; strong cryptographic/security knowledge; coding in C, Verilog/VHDL, scripting with Python/Perl/Ruby; Unix/Linux shell; excellent communication.
C, Verilog, VHDL, Unix, Linux, Perl, Python, Ruby, Makefile, Atlassian JIRA, Confluence
1d
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Senior FPGA Development Engineer
Boulder, Colorado, United States
$146k-$190k/yr OnsiteFull Time
Bachelor's degree in electrical or computer engineering; progressively responsible FPGA, ASIC, or digital-logic experience; expert VHDL, Verilog, or SystemVerilog; verification, implementation, and technical leadership expertise.
VHDL, Verilog, SystemVerilog, Git, Jira, Confluence, DOORS, Microsoft?, AMD Versal, UltraScale+, Zynq, Microchip PolarFire, PolarFire SoC, Lattice Nexus, SpaceWire, SpaceFibre, AXI, Ethernet, SPI, PCIe, JESD204, LVDS, DDR3, DDR4, ONFI NAND, eMMC, MRAM, UVM, cocotb, Python, Tcl
1mo
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Space Electrical Chief Engineer
Englewood, Colorado, United States
$141k-$252k/yr OnsiteFull Time
13+ YOEExtensive spacecraft electrical experience (system architecture, power, avionics, EEE parts), ability to obtain DoD clearance, 13+ years engineering experience (or equivalent), leadership of multidisciplinary teams, requirements and test oversight.
DOORS, SpaceWire, CAN, MIL STD 1553, Ethernet, FPGA, ASIC, HIL, EMC, EMI, MBSE, MIL STD 1540, MIL STD 461, NASA GEVS
1mo
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Engineer II - FPGA Verification
Westminster, Colorado, United States
$79k-$135k/yr OnsiteFull Time
2+ YOEBS in Engineering +2 years experience (Master's/PhD may substitute), FPGA/ASIC verification experience, SystemVerilog and UVM proficiency, object-oriented testbench design, coverage-driven verification, and eligibility to obtain Secret clearance; U.S. person required.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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Principal Electrical Engineer - Denver, CO
Denver, Colorado, United States
$130k-$209k/yr HybridFull Time
12+ YOEB.S. in Electrical Engineering, 12+ years designing complex electrical systems, system architecture experience, technical leadership and mentorship, mixed-signal/analog/digital expertise; medical device or regulated industry experience preferred.
FPGA, ASIC, HDL
1mo
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
1mo
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Senior FPGA Verification Engineer - $30K Sign On Bonus
Westminster, Colorado, United States
$97k-$165k/yr HybridFull Time
4+ YOEBS in engineering plus 4+ years related experience (or equivalent), strong FPGA/ASIC verification skills with System Verilog and UVM, coverage-driven verification, class-based constrained-random testbenches, and strong communication skills; eligible for U.S. security clearance.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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Senior PC Board Design Engineer
Austin or Colorado Springs or Markham
$123k-$210k/yr OnsiteFull Time
Strong high-speed PCB layout experience, expertise with Cadence Allegro and Constraint Manager, routing for PCIe/DP/Memory/XGMI, ASIC ball-outs, stackup/impedance control, PCB manufacturing knowledge, scripting (Pearl, C, C++). Bachelors/Masters in ECE preferred.
Cadence Allegro, Allegro, Constraint Manager, Pearl, C, C++, Valor, Valor ERF, CAM350, PCIe, DP, XGMI
1mo
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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