13 asic engineer jobs at 9 companies in Cotati, CA
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2mo
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Analog ASIC Architect
Austin or San Francisco
HybridFull Time
10+ YOEExperience in analog and mixed-signal ASIC architecture; BS and at least 10 years experience.
MATLAB, Python
2mo
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Analog ASIC Architect
Austin or San Francisco Bay Area
HybridFull Time
10+ YOEExperience in analog and mixed-signal ASIC architecture; BS and 10+ years of industry experience.
MATLAB, Python
2mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
1mo
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
4d
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Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
3w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
3mo
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Networking Operating System Firmware Engineer
San Francisco, California, United States
$266k-$445k/yr HybridFull Time
Networking OS firmware, NOS images, Linux kernel, switch ASICs, SAI; strong C/C++, Python, Go or Rust; experience with NOS stacks (SONiC, FRR) and OpenAI-scale infrastructure.
SONiC, FRR, Linux, SAI, ASIC_SDK, C/C++, Python, Go, Rust
1mo
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Sr. Staff, Instrument Software Engineer
South San Francisco, California, United States
$175k-$210k/yr OnsiteFull Time
10+ YOESenior staff-level software engineer with ~10+ years experience; expertise in C/C++/C#/Rust/TypeScript/Python, firmware and hardware integration, RTOS, memory management, and large-data performance optimization.
C#, C++, C, Rust, TypeScript, Python, Git, AWS, Azure, GCP, .NET, WPF, RTOS, SPI, USB, 1G/10G Ethernet, FPGA, ASIC
1d
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Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms
San Francisco, California, United States
OnsiteFull Time
15+ YOEBachelor's or master's in electrical or computer engineering or equivalent; 15+ years semiconductor program management experience across IP or ASIC programs; expertise in silicon lifecycle, cross-functional execution, schedules, risks, budgets, and vendors.
UCIe, Jira, Microsoft Project, Smartsheet, Confluence, Agile, Waterfall
2d
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System Engineering Lead - Wired Networking Hardware, eero
San Francisco, California, United States
$158k-$214k/yr OnsiteFull Time
8+ YOE5+ MgmtBachelor's degree and 8+ years in wired networking hardware design, including 5+ years leading hardware designs, networking ASIC integration, high-speed serial interfaces, PoE systems, and validation planning.
Networking ASICs, Ethernet PHYs, PoE, SFP, SerDes, PCB, Sigrity, PowerDC, SIwave, HyperLynx, EMI/EMC, UL/IEC 62368-1, IEEE, IPC
2mo
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PD - Sr Staff - Physical Verification Lead | Signoff & DRC
Bay Area, California, United States
OnsiteFull Time
15+ YOE15+ years ASIC physical verification experience; lead tapeouts; multi-foundry expertise across major nodes and packaging; strong DRC/LVS/DFM background; PV automation and signoff leadership.
Calibre, IC Validator, Python, Perl, Tcl, GDSII
1mo
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python