52 asic engineer jobs at 19 companies in Epping, NH
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
1w
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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
2mo
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ASIC/FPGA Verification Engineer IV
Denver or Highlands Ranch or Sunnyvale or Cambridge
$124k-$246k/yr OnsiteFull Time
5+ YOEBachelors in EE (or equivalent), 5+ years FPGA/ASIC verification experience, UVM/SystemVerilog/VHDL/Verilog expertise, experience with modern verification methodologies and tools, and ability to obtain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, Linux, Microsoft Project, JIRA, Python, OVM, VMM
2mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
2mo
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Senior ASIC Timing Engineer
Westford or Durham
$168k-$311k/yr OnsiteFull Time
4+ YOEBS in ECE (8+ yrs) or MS (4+ yrs) in synthesis and timing; hands-on STA, timing constraints, ECOs, physical design and synthesis/LEC; experience with Synopsys PrimeTime or Cadence Tempus; Python, Tcl, Make scripting.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
2mo
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Mixed Signal ASIC Engineer
Boston, Massachusetts, United States
OnsiteFull Time
5+ YOEPhD in electrical engineering or equivalent industry experience; 5+ years designing analog/mixed-signal ICs; strong ADC/DAC, amplifiers; tape-out experience; Cadence or Synopsys tools; end-to-end IC development.
Cadence, Synopsys
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
3d
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ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$155k-$248k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3+ years of FPGA and embedded design experience, and proficiency with design, verification, CI/CD, and Linux tools.
Verilog, Vivado, Quartus, Jenkins, Docker, Git, Linux, LSF, ClearCase, Artifactory, SystemVerilog, UVM
1w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
1mo
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Senior Electrical Engineer
Wilmington, Massachusetts, United States
$115k-$173k/yr OnsiteFull Time
5+ YOEBS/MS in Electrical Engineering, 5+ years product development experience, motion control required, embedded microprocessors, PCB layout (Altium) experience, firmware/FPGA/Verilog knowledge, ability to support system-level design and testing.
PCB Layout Tools, Altium, PLD, FPGA, ASIC, Verilog
1mo
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Electrical Engineer - Hardware & Embedded Systems
Waltham, Massachusetts, United States
$100k-$116k/yr OnsiteFull Time
4+ YOEBachelor's in electrical/computer engineering, 4+ years relevant experience, 3+ years embedded systems, proficiency in Embedded C/C++, RTOS, hardware-software integration, control systems, and communication protocols (I2C, SPI, UART, CAN).
Embedded C/C++, RTOS, I2C, SPI, UART, CAN, MATLAB/Simulink, LabVIEW, PLCs, FPGA, ASIC, Git, IDEs, debuggers
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
1w
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Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
4w
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
2mo
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FPGA Design Engineer
Nashua or Manchester or New Hampshire or United States
$97k-$165k/yr OnsiteFull Time
4+ YOEEligible for Secret clearance; typically a Bachelor's + 4+ years (or equivalent). FPGA/ASIC design experience with VHDL/Verilog, testbench development, timing closure, revision control, lab testing, and strong communication/problem-solving skills.
VHDL, Verilog HDL, SystemVerilog, UVM, GIT, CVS, Clearcase, Subversion, Xilinx Vivado, Intel/Altera Quartus, ModelSim, QuestaSim, MATLAB/Simulink, Perl, Tcl, Python, shell, C/C++, ILA, ChipScope, SignalTap
1mo
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
2mo
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Senior Electrical Engineer - FPGA Design
Tewksbury or Marlborough
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen able to obtain/maintain Secret clearance; STEM bachelor's degree typically required; minimum 5 years relevant FPGA/ASIC design or verification experience with VHDL/Verilog/SystemVerilog; experience with Xilinx or Microsemi devices and integration/debug.
VHDL, Verilog, SystemVerilog, UVM, Xilinx, Microsemi, Veloce, ARM, MicroBlaze, Nios
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
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