16 asic engineer jobs at 5 companies in Euless, TX
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yrHybridFull Time
Lockheed MartinNYSE: LMT: Designs and manufactures global security and aerospace systems.
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yrRemoteFull Time
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
RTXNYSE: RTX: RTX provides advanced aerospace and defense systems and services.
2+ YOEU.S. citizen with active DoD Secret clearance, STEM degree and ≥2 years FPGA/ASIC experience (VHDL/Verilog/SystemVerilog), experience with AMD/Altera/Microchip toolchains, lab integration and verification skills.
VHDL, Verilog, SystemVerilog, AMD Vivado, Altera Quartus Prime Pro, Libero, High Level Synthesis (HLS)
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
0+ YOEBachelor's or Master’s in EE/CE, 0–3 years experience or internship in ASIC/SoC/DFT, familiarity with digital design and synthesizable RTL (SystemVerilog/Verilog), and ability to support DFT implementation, validation, and debug.
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
0+ YOEBachelor's degree in EE/CE (or Master's), 0–3 years ASIC/SoC or DFT experience, basic digital design knowledge, familiarity with SystemVerilog/Verilog and DFT concepts, and ability to support implementation, validation, and debug.
RTXNYSE: RTX: RTX provides advanced aerospace and defense systems and services.
0+ YOESTEM bachelor’s required typically; less than 2 years relevant experience; FPGA/ASIC design or verification (VHDL/Verilog/SystemVerilog); experience with AMD Vivado, Altera Quartus Prime Pro, or Libero; lab integration and debug; source control and design reviews.
VHDL, Verilog, SystemVerilog, AMD Vivado, Altera Quartus Prime Pro, Libero, UVM, High Level Synthesis (HLS)
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
5+ YOEBachelor's or Master's in EE/CE (or equivalent experience), 5+ years DRAM or ASIC DFT experience, strong DFT fundamentals (scan, MBIST, JTAG), RTL experience (SystemVerilog/VHDL), and familiarity with semiconductor test flows.
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
5+ YOEBachelor's/Master's in EE/CE or equivalent, strong digital design and DFT fundamentals (scan, MBIST, JTAG), RTL experience (SystemVerilog/VHDL), familiarity with semiconductor test flows, and 5+ years DRAM or ASIC DFT design/verification experience.
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
10+ YOE10+ years PDN design experience for SoCs/ASICs; proficiency with Cadence RedHawk, Ansys Totem, and Spice; experience with EM/IR analysis, floorplanning interactions, RTL-to-GDSII signoff flows; BS/MS in EE/CompE preferred.
Lockheed MartinNYSE: LMT: Designs and manufactures global security and aerospace systems.
STEM bachelor's degree, software development background, experience leading and hiring software engineers, strong C/C++ and FPGA/ASIC knowledge, software architecture/process expertise; Secret clearance and U.S. citizenship required.
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
5+ YOEBachelor's or Master's in EE/CE, 5+ years DFT/DFT verification experience in DRAM or ASIC, strong knowledge of scan, MBIST, JTAG and boundary scan, wafer probe/final test experience.