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215 asic engineer jobs at 34 companies in Texas

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ASIC Engineer, Architecture
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
8+ YOEBachelor's (or equivalent), 8+ years in ASIC/silicon engineering, 5+ years in performance modeling; proficiency in C++, Python, SystemC; experience with microarchitectural analysis for data center/AI workloads.
C++, Python, SystemC, SystemVerilog, VHDL
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2w
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
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3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
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Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
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Senior ASIC Physical Design Engineer
San Jose or Austin or Research Triangle Park
$165k-$241k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
1+ YOEDegree in Electrical or Computer Engineering with relevant ASIC experience (varies by degree), experience with EDA tools (Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus), STA experience, and Python scripting.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Static Timing Analysis (STA), Python, AI tools
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Sr Principal ASIC Design Engineer - Terawave
San Diego or California or Austin or Texas or Kent
$308k-$431k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
15+ YOEExperienced ASIC/SoC design and verification engineer with expertise in Verilog/SystemVerilog, DSP structures, ARM integration, interface protocols, FPGA flows, post-silicon bring-up; BS/MS in EE or related and 15+ years experience required.
Verilog, SystemVerilog, MATLAB, SystemC, C
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ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
Ericsson
EricssonNasdaq Stockholm: ERIC B: Global provider of telecommunications equipment and services.
Several years of RTL verification experience in IP/ASIC/SoC, deep SystemVerilog and UVM knowledge, testbench architecture, scripting (TCL/Python/Perl), Linux/GIT experience, and BS/MS in EE/CE or equivalent experience.
SystemVerilog, UVM, TLM, TCL, Python, Perl, Linux, GIT, LSF
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Retym
Retym: Developing coherent DSP silicon for AI data center infrastructure.
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
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Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
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ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
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3mo
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ASIC Design Engineer – Fabric/Interconnect
Austin, Texas, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBS in a relevant field with 3+ years of experience; knowledge of interconnect fabrics, RTL, and memory hierarchy; experience with synthesis, verification, and power/performance optimization.
RTL, Synthesis, Front-end tools
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2mo
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
Cornelis Networks
Cornelis Networks: High-performance networking solutions for AI and HPC datacenters.
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
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2mo
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ASIC RTL Design Engineer (784246)
Austin, Texas, United States
HybridFull Time
Ericsson
EricssonNasdaq: ERIC: Manufactures telecommunications equipment and provides networking services.
3+ YOEBS in Electrical or Computer Engineering; several years of hands-on RTL design experience; strong digital logic; proficient in C/C++, TCL, Python; SystemVerilog/Verilog/VHDL; CDC/STA knowledge; RTL linting/CDC tools; AMBA experience; EDA tool familiarity; Git/Linux.
SystemVerilog, Verilog, VHDL, C, C++, Python, TCL, EDA tools, SpyGlass, AMBA, Cadence, Mentor, Synopsys, Git, Linux
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Neuralink
Neuralink: Developing implantable brain-computer interfaces to restore human capabilities.
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
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ASIC Design Verification Engineer (Santa Clara, CA)
Santa Clara or Austin
$127k-$190k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
3+ YOE3+ years DV experience using UVM/assertion-based verification; experience verifying SoC/subsystems, caches, DDR, memory VIPs, DDR PHY, formal verification, PASIM, C++ and Python exposure; bachelor's/master's/PhD in science or engineering.
UVM, SystemVerilog, C++, Python, PASIM, UPF
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
Lockheed Martin
Lockheed MartinNYSE: LMT: Designs and manufactures global security and aerospace systems.
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale
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Senior ASIC Repair Engineer (Bitcoin Mining)
Pyote, Texas, United States
OnsiteFull Time
GoMining
GoMining: Provides NFT-based access to Bitcoin mining hashrate.
3+ YOE3+ years repairing Bitcoin mining equipment at component level; hands-on experience with Bitmain and Whatsminer/MicroBT units; SMD/BGA soldering, schematic reading, electronics and power systems diagnostics.
Bitmain S19 XP, Bitmain S21, Bitmain T21, Whatsminer M30++, Whatsminer M50 series, MicroBT, SMD, BGA
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Senior Staff Application Engineer
Austin, Texas, United States
OnsiteFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
10+ YOEMS in Engineering required, 10+ years in power management, experience with firmware-enabled products and large-scale ASIC/SoC power, multiphase DC/DC converters, mixed-signal ICs, control loop theory, FPGA prototyping, lab equipment and automation.
FPGA, ASIC, Network Analyzer, Oscilloscope, Waveform Generator
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