1mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
1mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$201k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering (or equivalent), 3+ years ASIC/FPGA verification experience using UVM/OVM/VMM, HDL (VHDL/Verilog/SystemVerilog), ability to obtain DoD Secret clearance (US citizenship required); scripting (Perl/TCL/Python) and leadership experience preferred.
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Perl, TCL, Python, Linux
1mo
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ASIC/FPGA Design Engineer IV, TS/SCI Clearance
Boulder or King of Prussia or Littleton or Louisville or Sunnyvale
$124k-$246k/yr OnsiteFull Time
5+ YOEMust be US citizen with active Top Secret clearance, BS in Electrical Engineering or equivalent, 5+ years experience in ASIC/FPGA design/debug/verification, leadership and project management skills, and familiarity with project tools.
Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
1mo
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ASIC/FPGA Verification/Emulation Engineer III
Sunnyvale or Highlands Ranch or Littleton or King of Prussia
$101k-$201k/yr OnsiteFull Time
3+ YOEBS in Computer or Electrical Engineering (or equivalent), 3+ years professional verification experience, HDL (VHDL/Verilog/SystemVerilog) and UVM experience, emulation experience (Zebu or HAPS), ability to obtain Secret clearance and US citizenship required.
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, HDL, Zebu, HAPS, Linux
1mo
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ASIC/FPGA Engineering Associate Manager
King of Prussia, Pennsylvania, United States
$124k-$246k/yr OnsiteFull Time
9+ YOE2+ MgmtB.S. in EE/Computer Engineering or equivalent; prior program/project management and SOC/ASIC/FPGA design or verification experience; U.S. citizenship and ability to obtain DoD Secret clearance; 9+ years preferred.
Microsoft Project, Microsoft Office, Atlassian JIRA, AMD / Xilinx Versal, Earned Value Measurement System (EVMS)
3mo
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ASIC Design Verification Technical Leader
Carlsbad or Allentown
$164k-$235k/yr OnsiteFull Time
8+ YOEBachelor's or higher in Electrical/Computer Engineering; 8+ years ASIC design verification or 6+ with masters; strong SystemVerilog/UVM; leadership experience; scripting (Python, Perl, TCL, Shell).
SystemVerilog, UVM, Python, Perl, TCL, Shell
4w
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM
2mo
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FPGA Engineer
Exton, Pennsylvania, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years FPGA/ASIC in regulated environments; proficient in Verilog/VHDL; Xilinx Vivado; DO-254 familiarity; hardware debugging; cross-functional collaboration
Verilog, VHDL, Xilinx Vivado, RTL simulation, ModelSim/Questa, DO-254 knowledge, I2C, SPI, JTAG, Ethernet, PCIe
6d
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Engineer II-Design
Allentown, Pennsylvania, United States
OnsiteFull Time
2+ YOE2+ years RTL design experience for ASIC, Bachelor’s in EE/CE/CS required, SystemVerilog and scripting (TCL/Perl/Python), Linux, static timing and simulation experience, US citizenship or permanent residency required.
SystemVerilog, Verilog, TCL, Perl, Python, LINUX, FPGA
1mo
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
1mo
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Engineering Planner (Project Engineer)
Highlands Ranch or King of Prussia or Sunnyvale
$70k-$140k/yr OnsiteFull Time
US citizen able to obtain DoD Secret clearance. Experience or coursework in FPGA/ASIC design and HDL (VHDL, Verilog, SystemVerilog). Proficiency with Microsoft Project and JIRA. BS in EE preferred.
Microsoft Project, JIRA, VHDL, Verilog, SystemVerilog
4w
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FPGA/Firmware Engineers in NY, NJ & PA
Liverpool or Owego or Syracuse or Moorestown or King of Prussia
$101k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in STEM, 5+ years engineering experience, FPGA/ASIC/firmware experience, U.S. citizenship and ability to obtain/maintain Secret clearance, experience with VHDL/Verilog, C/C++, Python, FPGA tools and PCB tools.
C, C++, Assembly, Python, Perl, VHDL, Verilog, Altium, Cadence, Eagle, Vitis HLS, Vivado, Quartus, Git, SVN, PCIe, AXI, SPI
2mo
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Principal Engineer – Network Evolution Architecture
Philadelphia, Pennsylvania, United States
HybridFull Time
10+ YOE Lead strategic architecture and system design for next-generation access and transport technologies; evaluate hardware/software architectures; design RF/optical networks; develop PoCs; collaborate with partners.
FPGA, ASIC, Python, RF, Optical networking, WiFi, O-RAN