26 asic engineer jobs at 7 companies in Isleton, CA
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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Staff/Principal Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEB.S. in EE/CS or equivalent, 6+ years verification experience, RTL debugging, scoreboarding, code coverage analysis, test-plan development; System-Verilog/UVM expertise preferred; familiarity with C and emulation advantageous.
System-Verilog, UVM, C, Claude-Code, RTL
1w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
2w
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Senior Software Engineer - VSD - Freemont CA Hybrid
Fremont, California, United States
$130k-$233k/yr HybridFull Time
10+ YOEMS in EE/CE/CS,10+ years designing and deploying optimization algorithms for EDA, ASIC/FPGA expertise, proficiency in C/C++ and Python, strong software engineering and communication skills.
C, C++, Python
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python
2mo
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Test & Debug Technician (Swing Shift)
Newark, California, United States
$27-$33/hr OnsiteFull Time
2+ YOEAssociate's degree in engineering/electronics or equivalent, 2+ years SMT/PCBA experience, proficiency with debugging BGA/FPGA/ASIC circuits, familiarity with communication protocols and test equipment, and ability to perform failure analysis.
Oscilloscope, X-ray machine, Flying Probe (Takaya), Agilent 3070 ICT, Multimeter, LCR meter, RS-232, RS-485, I2C, SPI, SMBUS, JTAG, SWD, Boundary Scan
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