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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
2d
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
3mo
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ASIC Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
10+ YOEBS and 10+ years of relevant industry experience; Verilog RTL design experience.
Verilog, RTL, Synthesis, EDA, Front end tools
1mo
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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors/Masters in EE/CS/CE or equivalent, 5+ years verification experience, strong SystemVerilog and C/C++ skills, verification methodology experience (UVM, constrained-random, coverage, assertions), familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Semiformal Verification (SFV), Perl, Python
16h
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
16h
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
3mo
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Hardware Design Engineer
Hillsboro, Oregon, United States
$107k-$199k/yr HybridFull Time
5+ YOEStrong SystemVerilog/Verilog RTL design, ASIC/FPGA experience, RTL verification, scripting, 5+ years, BSEE.
SystemVerilog, Verilog, Questa, Incisive, VCS, Python, Perl, Tcl
1d
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Implant Software Staff Engineer (62275)
Lake Oswego, Oregon, United States
OnsiteFull Time
8+ YOE8+ years embedded software experience, BS/MS in engineering, experience with 8-bit microcontrollers, C and assembly, medical device/regulatory experience, strong communication and problem-solving.
C, Assembly, RTOS, ASIC
1mo
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Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with 3+ to 8+ years technical engineering experience depending on degree, experience in ASIC/SoC verification, UVM/SystemVerilog/Verilog and C proficiency, ability to pass Microsoft security screening.
UVM, C, Verilog, System Verilog
3w
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Integrated Circuit Design Verification Engineer
Vancouver, Washington, United States
$173k-$259k/yr OnsiteFull Time
10+ YOE10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
2mo
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Senior Applications and Solutions Engineer - Foundry Services
Phoenix or Santa Clara or Hillsboro
$122k-$232k/yr HybridFull Time
4+ YOEUS citizen; ability to obtain US government security clearance; 4+ years CMOS/low-power/multi-voltage domain; ASIC design and verification experience; scripting in Python/Perl/Tcl.
Cadence, Synopsys, UPF/CPF, VCLP, Conformal LP, Python, Perl, Tcl
1mo
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Field Applications Engineering
San Jose or Hillsboro
OnsiteFull Time
7+ YOE7+ years FPGA/ASIC design experience with VHDL/Verilog/SystemVerilog and tool experience (Radiant, Diamond, Quartus, Vivado); Bachelor's in Electrical Engineering; strong communication and presentation skills; customer-facing experience and periodic travel availability.
VHDL, Verilog, SystemVerilog, Radiant, Diamond, Quartus, Vivado
3w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
2w
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FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, Oregon, United States
$171k-$274k/yr OnsiteFull Time
12+ YOE5+ MgmtB.S./M.S. in EE,12+ years digital ASIC/FPGA design,5+ years project lead,verilog/RTL,Cadence and static timing tools,PCIe/DDR/AXI/SERDES experience,excellent communication and presentation skills.
verilog, RTL, Cadence, Vivado, Quartus, UVM, Linux, Windows, PCIe, DDR3, DDR4, DDR5, AXI, Ethernet, SPI, SERDES, Lint, CDC, ATE
1mo
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
3d
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Technical Program Management Lead (Member of Technical Staff)
Vancouver or Chandler or California
HybridFull Time
10+ YOEBachelor's in engineering or CS, 10+ years program management in semiconductor/ASIC/hardware, strong silicon development knowledge, vendor management, schedule and risk management, experience with Jira/Confluence/Smartsheet/Microsoft Project.
Jira, Confluence, Smartsheet, Microsoft Project
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