57 asic engineer jobs at 11 companies in Kenmore, WA
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Senior ASIC Emulation Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python,Perl,TCL), firmware and C/C++ integration, pre/post-silicon debug.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C/C++, HAPS, Protium, APB, AHB, AXI, JTAG, SPI, PCIe, Ethernet, USB
1d
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ASIC Engineer - Early Career
Seattle or Texas or California
$129k-$181k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
0+ YOECompleted or final-year BS/MS in electrical or computer engineering; project or coursework experience with Verilog/SystemVerilog, digital logic, and verification concepts. Strong problem-solving, communication, and teamwork skills required.
Verilog, SystemVerilog, UVM, Python, Perl, Tcl, VCS, Xcelium, Questa, GitHub, AXI
1mo
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ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
3mo
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FPGA/ASIC Design Engineer (Silicon Engineering)
Irvine or Redmond
$125k-$145k/yr OnsiteFull Time
1+ YOEBachelor’s in EE/CE/CS/Physics; 1+ years RTL design (SystemVerilog/Verilog/VHDL); strong Python/C/C++, and PCB/lab experience.
Verilog/SystemVerilog, VHDL, Python, C/C++, Bash, HDL simulators, Spyglass, Vivado, Quartus, AXI/APB/AHB protocols
2mo
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Lead ASIC Design Verification Engineer, Amazon Leo
San Diego or Sunnyvale or Redmond
$159k-$215k/yr OnsiteFull Time
7+ YOEMaster's or PhD in Electrical Engineering; 7+ years verification experience; 5+ years in UVM, C/C++, and scripting.
UVM, C/C++, SystemC, DPI-C, Matlab, Scripting
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ASIC/FPGA Mid-Level Manager - Design & Verification
Tukwila, Washington, United States
$182k-$246k/yr OnsiteFull Time
10+ YOEBachelor's degree, 10+ years of ASIC/FPGA design or verification experience, SystemVerilog, hardware integration and testing, team leadership, project tracking, U.S. citizenship, and ability to obtain Secret clearance.
SystemVerilog, FAA DO-254, earned value
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
5+ YOERequires a doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years, or equivalent experience in electrical, computer, or related engineering. Preferred expertise includes digital design, RTL, NoC, ASIC/SoC, synthesis, and post-silicon debug.
Intellectual Property (IP), Register Transfer Level (RTL), System on Chip (SOC), Verilog, SystemVerilog, Clock Domain Crossing (CDC), NoCs, ASIC, CPU
3w
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Electrical Engineer II
Lynnwood, Washington, United States
$102k-$119k/yr OnsiteFull Time
3+ YOEBA/BS in engineering, 3+ years relevant experience, knowledge of analog/digital/micro-electronics, VHDL, power and ASIC design, and experience with testing and product development.
VHDL
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Lead Radiation Effects Engineer
Seattle, Washington, United States
$185k-$215k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering, physics, nuclear engineering, or related field; 5+ years in radiation-effects engineering for high-reliability electronics; radiation modeling, testing, analysis, and automation experience required.
OMERE, Matlab, Python, Altium, KiCAD, OrCAD, FPGA, ASIC
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
1mo
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Cloud Acceleration Engineer – DPU & AI Infra
Seattle, Washington, United States
OnsiteFull Time
2+ YOE2+ years industry experience (PhD exception), proficiency in C/C++ and Linux systems, strong understanding of compute/network architecture and OS, experience in software-hardware co-design or high-performance networking or AI/ML systems.
C/C++, Linux, OVS, SR-IOV, eBPF, DPDK, FPGA, ASIC, GPU, CUDA, NCCL
2w
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Director, Network Development
Nashville or Seattle or United States or Austin or Reston or Santa Clara
$146k-$306k/yr OnsiteFull Time
10+ YOE10+ years experience leading network product engineering, expertise in switching/routing/optical/ASIC platforms, vendor partnerships, hardware qualification, and cross-functional execution.
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