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Timing Design Engineer
Melbourne, Florida, United States
OnsiteFull Time
2+ YOEBachelors in Electrical Engineering; 2+ years ASIC timing constraints and timing closure; experience with STA tools (Primetime); scripting (Tcl/Perl); strong collaboration skills.
Primetime, SDC constraints, scripting (Tcl, Perl), CAD tools, Synthesis, DFT, backend tools
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
2mo
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Sr. Specialist, Electrical Engineer - FPGA (37019)
Palm Bay, Florida, United States
OnsiteFull Time
6+ YOEActive experience designing and verifying FPGA/ASIC for wireless communications, DSP, modems, and networking; bachelor's degree or equivalent experience; 6+ years relevant experience; SECRET clearance required.
Vivado, Quartus, MATLAB, Simulink, VHDL