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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
2mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
2mo
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Product Planning Engineer-ASIC/SoC
San Jose, California, United States
$140k-$240k/yr OnsiteFull Time
Experience in product planning for next-generation AMD Adaptive and Embedded Computing products; strong collaboration across architecture, design, and product teams; ability to drive technical decisions independently.
Power estimation, Power delivery, Thermal solutions, FPGA, Adaptive SoCs, Embedded x86, ASICs, ASSPs, Product planning, Data analysis
2mo
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Principal Hardware Engineer, DSP
Los Gatos, California, United States
HybridFull Time
10+ YOE10+ years in DSP/hardware signal processing; coherent/optical DSP; MATLAB/Python/C/C++; hardware/FPGA/ASIC validation; strong collaboration and communication.
MATLAB, Python, C/C++, FPGA, ASIC
3w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
1mo
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
2mo
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IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Strong RTL design skills, FPGA/ASIC knowledge, and collaboration across global teams. Proficiency in Verilog/SystemVerilog and scripting; excellent English communication.
Verilog, SystemVerilog, UVM, OVM, Python, Perl, Tcl, Shell, EDA Tools, Synopsys, Primetime, VCS, Cadence Virtuoso
2mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
2mo
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Principal DV Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
10+ YOE10+ years of design verification experience in semiconductors; expert Verilog/SystemVerilog/UVM; C/C++ and Python; leadership experience; ability to verify ASICs and lead verification efforts.
Verilog, SystemVerilog, UVM, VHDL, C++, Python, Perl, Bash
2mo
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Senior EM/IR Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOE8+ years EM/IR analysis for complex ASICs/SoCs; power integrity; PDN design and sign-off; Verilog/SystemVerilog/UVM; scripting (Python/Tcl); experience with Cadence Voltus and Synopsys RedHawk.
Cadence Voltus, Synopsys RedHawk, Verilog, SystemVerilog, UVM, VHDL, Tcl, Python
2mo
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Director Silicon Design Engineering
San Jose, California, United States
HybridFull Time
15+ YOE5+ Mgmt15+ years ASIC/semiconductor leadership; strong hands-on design and program management; FPGA experience a plus; deep ASIC development lifecycle knowledge.
RTL, ASIC, Analog Design, Digital Design, Tapeout, Post-Silicon Validation
1w
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Sr. Manager System Architect
San Jose or Santa Clara
$158k-$271k/yr HybridFull Time
Bachelor's in engineering required; proven experience designing wired subsystems with FPGA/SoC/ASIC, RTL/FPGA tools, Ethernet and networking expertise, system architecture, benchmarking, power/thermal optimization, project management, and AI/ML tool use.
FPGA, SoC, ASIC, RTL, FPGA tools, AI ML tools
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Fellow - FPGA architecture
San Jose, California, United States
$235k-$402k/yr OnsiteFull Time
Expertise in FPGA configuration and Partial Reconfiguration, bitstream and boot flows, configuration security, ASIC/SoC design experience, and leadership in architecture definition and mentorship.