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Sr. ASIC Layout Design Engineer
Goleta, California, United States
$114k-$151k/yr OnsiteFull Time
10+ YOE10+ years in analog/mixed-signal IC layout; Cadence Virtuoso XL; Calibre DRC/LVS; 180/130/75nm nodes; GDSII/PDK; programming skills (SKILL, TCL, Shell, Python).
Cadence Virtuoso XL, Cadence tools, Calibre, LVS, DRC, GDSII, PDK, Siemens, Parasitic extraction, Python, SKILL, TCL, Shell
1w
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Principal Digital Engineer
Woodland Hills, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance; extensive experience in high-speed digital design and verification, FPGA/SoC/ASIC implementation (VHDL/Verilog), hardware requirements and verification processes.
VHDL, Verilog, System Verilog, UVM, MATLAB, Simulink, Hardware-In-Loop, FPGA, SoC, ASIC, DO-254
2w
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Senior Principal Digital Engineer
Woodland Hills, California, United States
$156k-$235k/yr OnsiteFull Time
4+ YOEU.S. citizen with active Secret clearance; STEM degree (BS/MS/PhD) with relevant experience (min 4+ yrs depending on degree); experience in high-speed digital design, FPGA/SoC/ASIC (VHDL/Verilog), design verification, and hardware implementation.
VHDL, Verilog, System Verilog, UVM, FPGA, SOC, ASIC, MATLAB, Simulink, Hardware-In-Loop, DO-254
2w
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Manager Digital Engineering 2
Woodland Hills, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOESTEM degree with 6–8+ years relevant experience, experience leading technical teams, digital design/verification knowledge (FPGA/SoC/ASIC), PLM experience, ability to obtain/maintain U.S. security clearance, U.S. citizenship required.
FPGA, SoC, ASIC, Product Lifecycle Management (PLM), Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW \u00096 Active Workspace, System Verilog, UVM, Hardware-In-Loop, MATLAB, Simulink, DO-254, RCCAs, BOE, EMV S