47 asic engineer jobs at 20 companies in Rio Vista, CA
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years ASIC design experience; strong Verilog/SystemVerilog; timing/room for leadership; knowledge of EDA tools; Python/Perl a plus.
Verilog, SystemVerilog, EDA tools, Python, Perl
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
2mo
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Staff/Principal Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEB.S. in EE/CS or equivalent, 6+ years verification experience, RTL debugging, scoreboarding, code coverage analysis, test-plan development; System-Verilog/UVM expertise preferred; familiarity with C and emulation advantageous.
System-Verilog, UVM, C, Claude-Code, RTL
2w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1mo
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
13h
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SMTS Silicon Design Engineer
Folsom, California, United States
$156k-$268k/yr OnsiteFull Time
4+ YOEMaster's degree in VLSI, electronics, computer, or electrical engineering plus 4 years of related experience; alternatively, bachelor's degree plus 6 years. Requires signal integrity, circuit design, validation, debugging, product cycles, and front-end EDA experience.
ASIC, Front-End EDA
1d
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Electrical Engineer
San Francisco, California, United States
$225k-$260k/yr OnsiteFull Time
Deep complex electronics design experience through manufacturing transfer; advanced mixed-signal, analog, power, high-speed digital, SI/PI, clocking, and grounding expertise; Python and C/C++ proficiency; hands-on test and debugging experience.
ASIC, FPGA, MCU, Python, C, C++, oscilloscopes, spectrum analyzers, network analyzers, logic analyzers, electronic loads, precision sources/meters, DAQ
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
3mo
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Networking Operating System Firmware Engineer
San Francisco, California, United States
$266k-$445k/yr HybridFull Time
Networking OS firmware, NOS images, Linux kernel, switch ASICs, SAI; strong C/C++, Python, Go or Rust; experience with NOS stacks (SONiC, FRR) and OpenAI-scale infrastructure.
SONiC, FRR, Linux, SAI, ASIC_SDK, C/C++, Python, Go, Rust
2mo
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Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
2d
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Associate Engineer - Firmware
Pleasanton, California, United States
$107k-$141k/yr OnsiteFull Time
Bachelor's or master's degree in electrical engineering, computer engineering, or computer science; C/C++ embedded firmware, RTOS or bare-metal, Python or Perl, lab equipment, debugging, and U.S. work authorization required.
C, C++, Python, Perl, RTOS, GitHub, ST microcontrollers, ASIC, oscilloscopes, function generators, voltmeters, debuggers, simulation tools, PID, TCP, UDP, UART, SPI, I2C, Assembly, lwIP, SoC, FPGA
3w
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Senior Software Engineer - VSD - Freemont CA Hybrid
Fremont, California, United States
$130k-$233k/yr HybridFull Time
10+ YOEMS in EE/CE/CS,10+ years designing and deploying optimization algorithms for EDA, ASIC/FPGA expertise, proficiency in C/C++ and Python, strong software engineering and communication skills.
C, C++, Python
1w
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Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms
San Francisco, California, United States
OnsiteFull Time
15+ YOEBachelor's or master's in electrical or computer engineering or equivalent; 15+ years semiconductor program management experience across IP or ASIC programs; expertise in silicon lifecycle, cross-functional execution, schedules, risks, budgets, and vendors.
UCIe, Jira, Microsoft Project, Smartsheet, Confluence, Agile, Waterfall
3w
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Senior Software Engineer - VSD - Freemont CA Hybrid
Fremont, California, United States
$130k-$233k/yr HybridFull Time
10+ YOEMS in EE/CE/CS,10+ years designing and deploying optimization algorithms for EDA, expertise in ASIC/FPGA tools, proficiency in C/C++ and Python, container experience, strong communication and presentation skills.
C/C++, Python
4d
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Silicon Architect
San Francisco, California, United States
$198k-$233k/yr HybridFull Time
10+ YOE10+ years in semiconductor definition, architecture, SoC/ASIC development, or system architecture for high-volume consumer electronics; expertise in low-power design, semiconductor flows, vendors, and technical leadership.
SoC, ASIC, RTL, CPUs, NPUs, DSPs
3d
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Ethernet Product Marketing Engineer
Hillsboro or Folsom or Santa Clara or Phoenix
$138k-$266k/yr HybridFull Time
5+ YOEBachelor's degree in business, marketing, or a related field; 5+ years of related experience in technical, networking, cloud, telecommunications, or data center industries and portfolio marketing strategy.
Ethernet, Cloud, ASIC, SoC
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