2mo
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Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
1mo
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOE15+ years hands-on ASIC/SoC/IO architecture experience; strong PCIe/UCIe/CXL, DMA know-how; ML/LLM aware; memory hierarchy optimization; ARM/x86/RISC-V host interactions.
PCIe, UCIe, CXL, DMA, NoC, HBM, GPU, TPU, xPU, NVMe
1mo
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AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
7+ YOE7+ yrs experience in Computer/Electrical Engineering; 5+ yrs for Masters; 3+ yrs for PhD; architecture authoring experience; PCIe/UCIe/CXL, DMA subsystems know-how.
PCIe, UCIe, CXL, NoC, DMA, HBM, NVLink, CUDA
1w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
3w
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Software Engineering Technical Leader
Milpitas, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in CS/EE/Electronics (or related) with considerable experience (varies by degree), strong expertise in C/C++ and Linux, experience with coherent optics, PHY/SerDes, ASIC/NPU, DSP, CMIS/SFF familiarity, proven architecture and cross-functional leadership.
C, C++, Linux, CMIS, SFF, Cisco Silicon One, IOS-XR, SONiC, FBOSS, DSP, ASIC, NPU, PHY, SerDes, FEC, ZR, OpenZR+, DWDM
1mo
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Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
3w
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Senior Software Engineer
Milpitas, California, United States
$165k-$241k/yr HybridFull Time
1+ YOEDegree in CS, EE, or related plus relevant experience (1–7+ years depending on degree); proficiency in C, C++, Python; embedded Linux, optics and NPU/ASIC integration; familiarity with CMIS/SFF and NOS platforms.
C, C++, Python, Linux, IOS-XR, SONiC, FBOSS, CMIS, SFF
1w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
2w
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Product Engineer, Tessent logic test
Wilsonville or Fremont or Ottawa or Saskatoon or North America
$90k-$162k/yr HybridFull Time
1+ YOEBS in EE/CS/CE required; 1-3 years DFT/ASIC experience; proficiency in Linux/Windows and Tcl or Python; strong problem-solving, communication, and ability to work with customers and cross-functional teams. Subject to U.S. export control.
Tessent, Linux, Windows, Tcl, Python, Verilog, SystemVerilog, VHDL
1mo
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Software Engineering Technical Leader
Milpitas, California, United States
$184k-$264k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CS (10+ yrs) or Master's (8+ yrs); experience with C, C++, Python, Linux, device drivers, embedded systems, and ASIC/FPGA bring-up; experience with Sonic/ONIE/BMC/IPMI/Redfish; strong debugging and communication skills.
C, C++, Python, Linux, Sonic, ONIE, BMC, IPMI, Redfish, GDB, KGDB, CMIS, SFF, SFP, QSFP, I2C, SPI, UART, PCIe, GPIO
3w
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Applications Engineering Consultant – FPGA Prototyping Justification - Job Detail | Careers Marketplace - Siemens
Austin or Fremont or San Diego or Santa Clara or Tempe or Wilsonville
$147k-$293k/yr HybridFull Time
7+ YOE7+ years in design/verification/simulation/emulation/prototyping or applications engineering; BS/MS in EE/CE/CS; experience with SystemVerilog/Verilog/VHDL, FPGA/ASIC flows, scripting (Perl/Python/shell), and FPGA tools (proFPGA, HAPS, Vivado, Quartus).
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, shell, Makefiles, XML, JSON, Questa, Incisive, VCS, OVM, UVM, proFPGA, HAPS, Xilinx Vivado, Altera Quartus
2mo
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Software Engineering Technical Leader, Ethernet Switching
Milpitas, California, United States
$184k-$264k/yr HybridFull Time
10+ YOEBS+10 years or MS+8 years or PhD+6 years in C/C++ and Python; embedded/router/switch software; debugging with GDB; SDLC and L2/L3/ACL/QOS; SDK development on networking ASICs; traffic generators (IXIA/Spirent).
C, C++, Python, GDB, SDK, IXIA, Spirent, Networking ASICs, NPU, DPU
1w
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Senior/Principal R&D Digital Systems Security, Hybrid
Albuquerque or Livermore
$140k-$281k/yr HybridFull Time
5+ YOEBachelor's plus 5 years relevant experience (or equivalent), ability to obtain DOE Q-level clearance, expertise in hardware/software security, formal methods, and familiarity with secure-system design and verification.
RocQ, Lean, C, C++, Java, Python, Rust, Assembly, ASIC, FPGA, NIST, CNSS