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Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
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Analog ASIC Design Engineer
Boulder or Beaverton
$149k-$277k/yr OnsiteFull Time
5+ YOEBSEE/MSEE and 5+ years analog/mixed-signal IC design experience, proficiency with ASIC design tools, layout and RF analysis, strong communication, willingness to travel domestically, must be a U.S. Person.
Ansys HFSS, Cadence EMX
1mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
2mo
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ASIC/FPGA Design Engineer IV, TS/SCI Clearance
Boulder or King of Prussia or Littleton or Louisville or Sunnyvale
$124k-$246k/yr OnsiteFull Time
5+ YOEMust be US citizen with active Top Secret clearance, BS in Electrical Engineering or equivalent, 5+ years experience in ASIC/FPGA design/debug/verification, leadership and project management skills, and familiarity with project tools.
Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
3w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2mo
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Principal Engineer, Firmware
Longmont, Colorado, United States
$161k-$275k/yr OnsiteFull Time
7+ YOELead firmware architecture for SSDs; 7+ years embedded firmware; C/C++, Python; ASIC/FPGA bring-up; strong communication.
C, C++, Python
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Staff FPGA Design Engineer
Berthoud, Colorado, United States
$150k-$180k/yr OnsiteFull Time
10+ YOEB.S. in Electrical Engineering with 10+ years in electronics hardware and ASIC/FPGA development for flight avionics; experience with mixed-signal design, VHDL/Verilog/SystemVerilog, timing closure, EMI/EMC, and hardware verification.
VHDL, Verilog, SystemVerilog, Python, TCL, Xilinx, Microsemi, MATLAB, Simulink, SPICE, Altium, SystemVerilog UVM, C, C++, assembly language, Linux/Windows shell scripting, Cocotb
1mo
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Engineer II - FPGA Verification
Westminster, Colorado, United States
$79k-$135k/yr OnsiteFull Time
2+ YOEBS in Engineering +2 years experience (Master's/PhD may substitute), FPGA/ASIC verification experience, SystemVerilog and UVM proficiency, object-oriented testbench design, coverage-driven verification, and eligibility to obtain Secret clearance; U.S. person required.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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Senior FPGA Verification Engineer - $30K Sign On Bonus
Westminster, Colorado, United States
$97k-$165k/yr HybridFull Time
4+ YOEBS in engineering plus 4+ years related experience (or equivalent), strong FPGA/ASIC verification skills with System Verilog and UVM, coverage-driven verification, class-based constrained-random testbenches, and strong communication skills; eligible for U.S. security clearance.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
3w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
2mo
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Senior Site Technician - Bitcoin Mining
Cheyenne, Wyoming, United States
OnsiteFull Time
3+ YOE3+ years in Bitcoin mining site operations or similar high-density data environments; strong ASIC miner knowledge; electrical and low-voltage skills; networking basics; ability to read diagrams; excellent troubleshooting and communication; able to work outdoors and flexible shifts.
ASIC miners, networking equipment, PDUs, cooling systems, electrical distribution, diagnostics
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