1mo
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
1w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
3w
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEProven SystemVerilog RTL development in advanced nodes, 8+ years SoC experience, BSEE required (MSEE/PhD preferred), experience with PPA optimization, CDC/RDC, low-power design, and high-speed memory/SerDes protocols.
SystemVerilog
1w
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Digital Design RTL Engineer
Fort Collins or San Jose
OnsiteFull Time
Expert SystemVerilog RTL for advanced nodes, 8+ years experience, BSEE required (MSEE/PhD preferred), SoC integration experience, SerDes/DDR/HBM protocols, CDC/RDC, low-power and PPA optimization, timing closure and cross-team collaboration.
SystemVerilog
2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
2mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
3d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
3d
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
3d
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
1mo
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CPU Cores Validation Senior Staff Engineer
Fort Collins, Colorado, United States
$178k-$268k/yr HybridFull Time
Experienced silicon validation engineer with strong programming (x86 assembly, C/C++, Perl, Ruby, Python), HDL knowledge (Verilog/System Verilog), DFT/JTAG familiarity, lab validation experience, and BS/MS in EE/CS/CSE.
x86 assembly, C, C++, Perl, Ruby, Python, Verilog HDL, System Verilog, JTAG -1149.x, BIST, LSSD/MuxD, RTL, DFT
1mo
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FPGA DSP Engineer
Fort Collins, Colorado, United States
$143k-$191k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE or related; 12+ years FPGA design experience; expert in RTL (SystemVerilog/VHDL), Xilinx toolchains (Vivado/Quartus), DSP implementation on FPGAs; FPGA verification and timing closure experience; eligible for U.S. Secret clearance.
SystemVerilog, VHDL, Vivado, Quartus, MATLAB, Git, Xilinx
1mo
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Senior Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
$156k-$268k/yr OnsiteFull Time
Experienced VLSI physical design engineer with hands-on high-speed design, chip floorplanning, CTS, P&R, STA, parasitic extraction, IR drop/EM analysis, Verilog RTL comprehension, scripting (Perl, C, tcl), and use of AI agents; BS/MS in EE/CS/CSE preferred.
Verilog, Perl, C, tcl, AI Agents
5d
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Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
$106k-$183k/yr HybridFull Time
5+ YOEBS/MS in EE/CS/CSE plus 5+ years hardware design experience; hands-on high-speed VLSI design, Verilog RTL comprehension, chip floorplanning, CTS, STA, parasitic extraction, IR/EM analysis; Perl/C/tcl familiarity.
Verilog, Perl, C, tcl
3d
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Summer 2027 Intern - Hardware Engineering
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$34-$47/hr HybridInternship
0+ YOEEarly-career candidates pursuing or holding technical degrees in engineering or related fields; experience via coursework, internships, projects; familiarity with programming, embedded systems, digital logic, or hardware design; strong analytical and communication skills.
RTL, Verilog/SystemVerilog, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, CAD, Git, Linux, Microsoft Office, RTOS
2mo
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Solutions Architect
San Jose or Longmont
$203k-$348k/yr HybridFull Time
Experienced in FPGA/RTL, embedded systems, PCIe, DDR, Ethernet; strong C/C++, SystemVerilog.
SystemVerilog, Verilog, PCIe, CXL, DDR, Ethernet, AXI, Python, Tcl, Makefiles, Shell scripting, Linux kernel, IPC, RTOS, UVM, Palladium, Protium, Zebu
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