41 asic engineer jobs at 11 companies in Winnetka, CA
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2w
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
9+ YOEBachelor's degree in a related technical field and 9+ years of FPGA, ASIC, or SoC digital design experience; HDL, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
ASIC, FPGA, SoC, HDL, RTL
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
7+ YOEBachelor's degree in a related technical field and 7–9+ years of ASIC, FPGA, or SoC digital design experience; HDL development, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
HDL, RTL, ASIC, FPGA, SoC
2mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
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Manager, ASIC Design Engineering (Starshield Satellite Engineering)
Hawthorne, California, United States
$190k-$245k/yr OnsiteFull Time
5+ YOE2+ MgmtLead ASIC/FPGA design team; RTL/Verilog; 5+ years RTL/FPGA/ASIC; 2+ years management; Bachelor's in engineering.
Verilog, SystemVerilog, HDL simulators, VCS, Questa, IES, Spyglass, Xilinx Vivado, Altera Quartus II, Python, TCL, EDA tools
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
1w
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Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, California, United States
$192k-$308k/yr OnsiteFull Time
15+ YOE5+ MgmtBSEE, MSEE, or equivalent; 15+ years of semiconductor experience; 5+ years leading complex ASIC development; mixed-signal ASIC delivery, distributed teams, external partners, program management, risk management, and executive communication.
ASIC, ATE, EDA
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Hardware Engineer, Mid
El Segundo, California, United States
$62k-$141k/yr OnsiteFull Time
7+ YOE7+ years hardware engineering experience, bachelor’s in Electrical or Computer Engineering, Secret clearance, experience with avionics hardware reviews (PDR/CDR/TRR), requirements and verification development, risk management, and up to 10% travel.
VHDL, Verilog, embedded C, ASIC, FPGA, DO-254
2mo
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Electrical Engineer III/IV
Burbank, California, United States
$125k-$177k/yr OnsiteFull Time
8+ YOEBA/BS in engineering, 8+ years relevant experience, US Person required for ITAR work, expertise in analog/digital/micro-electronics, VHDL, ASIC, DO-254/DO-160, magnetics, switching power supplies, hardware/software integration, and strong communication skills.
VHDL, DO-254, DO-160, Kaizen, 5S, Lean
1mo
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Principal Electronics Design Engineer
Garden Grove, California, United States
$140k-$190k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years electronic systems design experience, FPGA and embedded microprocessor design, GNSS/M-Code/SAASM, Ethernet/PTP, schematic capture, team leadership, ability to obtain secret clearance and U.S. citizenship.
FPGA, PWB, GNSS, M-Code, SAASM, Ethernet, Precision Time Protocol (PTP), SoC, SoM, ASIC
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Certification Systems Engineer, Lead
El Segundo, California, United States
$99k-$225k/yr HybridFull Time
10+ YOE10+ years DoD GPS software/system engineering; security IA; cryptography; leadership; TS/SCI desired; Bachelor's; Secret clearance.
GPS, FPGAs, ASIC, Cryptography, Information Assurance, Microsoft Office
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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