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ASIC Verification Engineer
Irvine or San Jose
$101k-$162k/yr OnsiteFull Time
3+ YOEEngineering degree (Bachelors/Masters/PhD) with 3+ years verification experience (varies by degree), proficiency in HDL and verification, C/C++, scripting, strong communication and teamwork.
SystemVerilog UVM, SystemVerilog, Verilog, VHDL, C, C++, Python, PERL, TCL
2w
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Sr. ASIC Design Verification Engineer (Silicon Engineering)
Irvine, California, United States
$165k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in electrical or computer engineering,5+ years design verification experience, proficiency with verification methodologies and scripting, strong problem-solving and OOP skills.
UVM, OVM, VMM, Python, RTL
1w
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Design Verification Senior Staff Engineer
Irvine or Santa Clara
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/Computer Engineering, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM and protocol knowledge, scripting (Python/Perl/Shell), debug and coverage skills.
System Verilog, UVM, Python, Perl, Shell, Palladium, Veloce
2w
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
3d
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Principal DFT Engineer (Silicon Engineering)
Irvine or Austin or Palo Alto
$210k-$340k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS,10+ years ASIC and DFT experience including scan insertion, ATPG, and post-silicon validation; strong RTL, debugging, and scripting skills.
Siemens Tessent, Perl, Python, Tcl, C+, Verilog, SystemVerilog, UPF, SDF, DRC, ATE