208 asic jobs at 38 companies in Lago Vista, TX
4w
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
3mo
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Analog ASIC Architect
Austin or San Francisco Bay Area
HybridFull Time
10+ YOEExperience in analog and mixed-signal ASIC architecture; BS and 10+ years of industry experience.
MATLAB, Python
13h
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Senior ASIC Verification Engineer (PCIe/CXL)
San Jose or San Diego or Austin or Longmont
$146k-$250k/yr HybridFull Time
Expertise in ASIC verification, Verilog, SystemVerilog, UVM testbenches, and Python or Perl scripting; experience with PCIe, CXL, NVMe, or Ethernet; bachelor's or master's degree in computer or electrical engineering.
FPGA, ASIC, UVM, Verilog, SystemVerilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
1mo
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
1w
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
2mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
1w
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ASIC Developer
Austin, Texas, United States
$117k-$175k/yr HybridFull Time
5+ YOESeveral years of complex ASIC/IP RTL design experience; expert SystemVerilog/Verilog skills; ASIC flow experience including linting, CDC, synthesis, and timing closure; DSP, FEC, or L1 algorithm hardware design experience.
SystemVerilog, Verilog, ASIC, IP, DSP, FEC, CDC
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
3mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
2w
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Senior ASIC Design Engineer – Clocks IP
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical Engineering or equivalent, 3+ years relevant ASIC/RTL experience, Verilog and Python skills, strong knowledge of logic optimization and PPA trade-offs, excellent collaboration and communication.
Verilog, python
1w
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ASIC Design Verification Engineer (784248)
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debugging; scripting with TCL, Python, or Perl; and a bachelor's or master's degree in engineering or equivalent experience.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, AMBA APB, AXI, ACE-Lite, CHI
5d
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ASIC Digital Design Engineer (HPC IP)
Austin, Texas, United States
$114k-$170k/yr OnsiteFull Time
5+ YOEBSEE or MSEE and 5+ years in ASIC digital design and verification, with RTL expertise, EDA tools, interface protocols, analytical problem-solving, and cross-functional communication skills.
RTL, Electronic Design Automation (EDA), PCI Express (PCIe), Compute Express Link (CXL), DDR, Ethernet
2mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
1mo
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Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
2mo
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Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
3mo
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
1w
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AI/ML driven ASIC Design and Implementation Automation Engineer
Austin, Texas, United States
OnsiteFull Time
1+ YOEBS or MS in a relevant discipline, Python/C++ programming, 1–2 years of AI/ML experience, optimization algorithms, Unix/Linux, Git, software debugging, and strong analytical and communication skills.
Python, C++, Unix, Linux, Git, BitBucket, SystemVerilog, Verilog, VHDL, DesignSync, Make, Splunk, Jenkins, LSF, CI/CD, SDC, UPF, LLMs, CNN, RNN, GraphNN, GenAI, Reinforcement Learning, Graph Neural Networks
2mo
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Staff Systems Engineer (Austin, TX, US)
Austin, Texas, United States
$114k-$220k/yr OnsiteFull Time
6+ YOEMSEE 6+ years or BSEE 8+ years with systems design; MATLAB; SystemVerilog, UVM, RNM; FPGA/ASIC design; lab equipment; RF/PLL knowledge.
MATLAB, SystemVerilog, UVM, RNM, FPGA, ASIC
6d
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Principal Ethernet Scale-Out Architect, AI Data Center
Santa Clara or Austin or San Diego
$192k-$305k/yr OnsiteFull Time
6+ YOERequires a science or engineering degree and 6–8+ years of ASIC or hardware architecture experience, plus expertise in Ethernet, datacenter networking, high-speed interfaces, DMA, virtualization, and system architecture.
Ethernet, UEC, RoCE/RDMA, NICs, SuperNICs, ASIC, DMA, InfiniBand, RoCEv2, PCIe, CXL, UCIe, SerDes, SONiC, SAI, OpenBMC, Linux