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Compiler Engineer - AI Inference
Santa Clara, California, United States
$152k-$242k/yr OnsiteFull Time
3+ YOEBS/MS (PhD preferred) in CS/CE or equivalent; 3+ years compiler experience; hands-on MLIR; strong C/C++ and Python skills; expertise in compiler optimizations, synthesis, and placement; strong communication.
MLIR, C, C++, Python
2mo
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Compiler Performance Engineer
Austin or Santa Clara or Seattle
$186k-$318k/yr HybridFull Time
Design and optimize compiler performance; analyze bottlenecks; improve performance of AMD applications and benchmarks; collaborate with vendor and internal teams.
C/C++, x86/x64 assembly, Auto-vectorization, Compiler toolchains, Git/Mercurial, vTune, WPA, MSVS Performance Profiler, Windows, Linux
6d
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Backend Compiler Engineer
Austin or Texas or Oregon or California or Redmond or Santa Clara
$124k-$242k/yr OnsiteFull Time
2+ YOE2+ years compiler code generation experience, B.S. in Computer Science/Engineering or equivalent, strong C++ skills, compiler optimization experience, good communication and documentation.
C++, CUDA, DirectX, OpenGL, Vulkan, PTX, LLVM, TableGen, LLVM IR, Machine IR (MIR)
1mo
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Compiler Engineer, GPU Acceleration
San Jose or Austin
$193k-$359k/yr HybridFull Time
Deep expertise in compiler frameworks (LLVM/MLIR), strong C++ and systems reasoning, runtime code generation and debugging, CI/CD experience; GPU programming (CUDA/PTX) and execution-engine/query-engine knowledge preferred.
LLVM, MLIR, C++, Velox, CUDA, PTX, Substrait, Presto, Watsonx.data, CI/CD
2mo
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Principal AI Compiler Engineer
Austin or San Jose or San Diego
OnsiteFull Time
MS/PhD in CS/EE or equivalent; deep AI compiler experience; graph optimization; MLIR/LLVM/TVM; C/C++ and Python; AI workloads; Scrum experience.
MLIR, LLVM, TVM, PyTorch, TensorFlow, ONNX, C++, Python, CUDA
3w
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FPGA Compiler (Placer) Engineer
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
6+ YOEBachelor's degree in EE/CE/CS, 6+ years in FPGA/ASIC CAD or EDA, strong algorithms and data structures, placement and physical design experience, proficiency in C/C++ and scripting (Python, Tcl).
C/C++, Quartus, Vivado, Python, Tcl
2mo
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RISC-V CPU Compiler Engineer
Santa Clara or Austin
$167k-$251k/yr OnsiteFull Time
2+ YOEDegree in EE/CE/CS (or related) with 2+–4+ years experience depending on degree; experience with LLVM, compiler optimization and code generation, C/C++; open-source contributions and CPU benchmarking.
LLVM, C/C++, GCC, glibc, assembler, linker, loader, SPECrate Integer, DCPerf
1mo
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Staff Compiler Engineer - PyTorch + Kernel DSLPLATE
San Jose, California, United States
$163k-$253k/yr OnsiteFull Time
10+ YOEBS with 10+ yrs, MS with 8+ yrs, or PhD with 5+ yrs; experience in Triton/Helion/MLIR/XLA/TVM/Inductor/IREE/CUTLASS; kernel DSL/IR design; MLIR; PyTorch backends; kernel autotuning; HPC/NUMA; open-source contributions.
Triton, Helion, MLIR, XLA, TVM, Inductor, IREE, CUTLASS, PyTorch, LLVM/MLIR
1w
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Machine Learning Engineer - AI Compiler Optimization
San Jose, California, United States
OnsiteFull Time
Proficient with AI compiler frameworks and GPU/NPU compilation optimization; experience with model import/conversion for PyTorch/TensorFlow and performance tuning for recommendation models.
Triton, MLIR, TVM, PyTorch, TensorFlow
3w
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Software Engineer I Compiler & Runtime
San Jose, California, United States
$135k-$165k/yr OnsiteFull Time
Degree in CS/CE/EE, experience developing embedded software, strong C/C++ and/or Python skills, understanding of data structures and algorithms, strong problem-solving and communication skills.
C, C++, Python, Rust, Zephyr, FreeRTOS, Linux, Git, CI/CD, ClearCompany Applicant Tracking System (ATS)
1mo
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
1mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent experience, 10+ years ASIC design experience, strong Verilog/SystemVerilog skills, knowledge of full digital ASIC flow and tools (Design Compiler, PrimeTime), Python for automation, and collaboration skills.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
1mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent with 10+ years ASIC design experience; expertise in Verilog/SystemVerilog; knowledge of full digital ASIC design flow; experience with Design Compiler and PrimeTime; Python and AI-assisted tool familiarity.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
1mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
1mo
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Sr. Analog Design Engineer
San Jose, California, United States
$120k-$180k/yr OnsiteFull Time
5+ YOEM.S. or Ph.D. in Electrical Engineering, 5+ years IC development with advanced CMOS (FinFET) experience; strong analog/mixed-signal circuit knowledge; proficiency with Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, and Verilog.
Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, Verilog
1w
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Solutions Engineer - AE
San Jose, California, United States
$172k-$191k/yr HybridFull Time
3+ YOEMaster's in EE or related, minimum 3 years EDA experience, proficiency with Innovus/Fusion Compiler/Tempus/PrimeTime, RTL-to-GDSII flows, Verilog/VHDL, Tcl scripting, strong communication and mentoring skills.
Tcl, Innovus, Fusion Compiler, Tempus, PrimeTime, Verilog, VHDL, GDSII
3mo
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Senior DSL Engineer
Santa Clara or Toronto or United States
HybridFull Time
BS in CS/CE or equivalent; extensive DSL design; compiler frontend; C++ with ARC concepts; type/shape inference; diagnostics; full software lifecycle; GPUs/accelerators familiarity.
C++, Compiler frontend, ARC (automatic reference counting)
2w
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Lead Engineer
Santa Clara, California, United States
$130k-$140k/yr OnsiteFull Time
8+ YOE8+ years physical design experience, expertise in Synopsys Fusion Compiler, low-power UPF methodologies, PPA optimization, strong Tcl/Python/Shell scripting, B.Tech/M.Tech in ECE/EE/VLSI, excellent communication and leadership.
Synopsys Fusion Compiler, Tcl, Python, Shell, PT, ICV, UPF
3mo
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GenAI Physical Synthesis Engineer
Austin or Santa Clara
HybridFull Time
3+ YOEExperience with GenAI frameworks, large language models, AI agents; synthesis tools (Fusion Compiler, Genus); TCL/Python/Perl scripting; BS + 3 years experience.
Fusion Compiler, Genus, TCL, Python, Perl, PyTorch, TensorFlow, Transformers, MCP, AutoGen, CrewAI, LangChain
1w
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Software Engineer - Model Infrastructure, TikTok Feeds
San Jose, California, United States
$156k-$388k/yr OnsiteFull Time
Bachelor's in CS or related field; understanding of GPU architecture and CUDA/CUTLASS/Triton Lang; experience with TensorFlow or PyTorch; familiarity with large-scale model training and DNN compilers (MLIR/XLA/TVM).
CUDA, CUTLASS, Triton Lang, TensorFlow, PyTorch, MLIR, XLA, TVM
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