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System FPGA Engineer
Santa Clara or Austin
$152k-$228k/yr OnsiteFull Time
5+ YOEBachelor's or higher in engineering/CS and 5+ years FPGA implementation and verification experience; proficiency in Verilog/SystemVerilog, Python, cocotb, git/GitHub, vendor FPGA toolchains; strong communication skills.
Python, git, GitHub, cocotb, Verilog, SystemVerilog, AMD/Xilinx Vivado/Vitis, Intel/Altera Quartus Prime, JTAG, oscilloscope
2mo
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Senior FPGA Engineer
Pleasanton, California, United States
$130k-$155k/yr OnsiteFull Time
5+ YOE5+ years FPGA engineering; HDL (Verilog/VHDL); Vivado/Questa; FPGA/SoC experience (AMD Zynq/UltraScale+); Bachelors/Masters in Electrical Engineering or related field; strong lab and communication skills; US export compliance eligibility.
Vivado, Questa, Verilog, VHDL, EDA tools, Git, Jira, Yocto, PetaLinux, OpenEmbedded
1w
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FPGA Engineer: Physical AI & Robotics
San Jose or Austin
HybridFull Time
Experienced FPGA/Adaptive SoC engineer with FPGA RTL and embedded software skills, familiarity with Verilog/SystemVerilog/VHDL, C/C++, Embedded Linux/Yocto, hardware debugging, and ability to work with customers on Physical AI solutions.
AMD Vivado, Vitis, Vitis HLS, Yocto, Verilog, SystemVerilog, VHDL, C, C++, PCIe, Ethernet, DisplayPort, MIPI CSI/DSI, USB, CAN, SPI, I2C, UART, GPIO, ROS 2, Git, JTAG, oscilloscope, protocol analyzer, logic analyzer
2mo
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FPGA Engineer (CA, San Jose)
San Jose, California, United States
HybridFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience in FPGA design and verification, proficiency in RTL/C/C++, Python; familiarity with VHDL/Verilog, hardware security, IP core development, and FPGA tools.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Altera, Versal, Stratix, Avalon, AXI, ACE, IP cores, cocotb, pyuvm
1mo
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FPGA Silicon Validation Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
3+ YOEBachelor's degree in electrical engineering (or related) plus 3 years' industry experience; FPGA architecture knowledge; experience with C and Python preferred; hands-on debug with oscilloscopes and power supplies; internship/work experience preferred.
FPGA, RTL, C, Python, oscilloscope, power supply
1mo
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Sr. FPGA Design Engineer
Milpitas, California, United States
$141k-$240k/yr OnsiteFull Time
3+ YOEExperience designing complex FPGA firmware; proficient with Xilinx/Intel FPGAs; HDL Verilog/SystemVerilog; FPGA tools (Vivado, VCS/Modelsim); timing analysis; knowledge of PCIe, DDR4, 10G, SPI, I2C; collaboration with hardware and software teams.
VCS, Modelsim, Vivado, Verilog, SystemVerilog, PCIe, Aurora, DDR4, 10G, SPI, I2C, embedded Linux
2mo
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Senior FPGA Design Engineer
San Jose, California, United States
$150k-$200k/yr OnsiteFull Time
5+ YOEStrong RTL FPGA design experience with Vivado and Protocompiler; FPGA/IP integration; 5+ years; PCIe/USB/Ethernet; BS/MS in EE/EECS/CS; English.
Vivado, Protocompiler, IP Integration, PCIe, USB, Ethernet, SPI
1mo
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Senior FPGA Prototyping Platform Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
7+ YOEBS in Electrical/Computer Engineering with 7+ years FPGA prototyping or MS with 5+ years; strong FPGA prototyping, lab, and debugging skills.
Synopsys Protocompiler, Xilinx Vivado, ChipScope, Oscilloscopes, Logic Analyzers, Protocol Analyzers
1mo
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Sr FPGA Design Engineer
Santa Clara, California, United States
OnsiteFull Time
8+ YOEBSEE or MSEE in EE/CE or related, 8+ years FPGA and embedded hardware development, strong Verilog/SystemVerilog/VHDL skills, experience with AMD/Xilinx/Intel/Altera/Lattice/Microchip platforms, PCB/PCBA and production experience, US work authorization required.
Verilog, SystemVerilog, VHDL, AMD/Xilinx, Intel/Altera, Lattice, Microchip, PCIe, Ethernet, USB, SPI, I2C, UART, CAN, DDR, DSP, Altium, Cadence Allegro, OrCAD, PCB, PCBA, DFM, DFT, EMC, EMI
1mo
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Senior FPGA Prototyping Platform Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
5+ YOEBS (or equivalent) with 7+ years or MS with 5+ years in FPGA prototyping; expertise in synthesis, place-and-route, timing closure, lab FPGA debug, and coordination with verification and software teams.
Synopsys Protocompiler, Xilinx Vivado, ChipScope, Synopsys HAPS, oscilloscopes, logic analyzers, protocol analyzers
1mo
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
2w
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Senior FPGA Design Engineer,( Nextest, San Jose, CA)
San Jose, California, United States
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in Electrical Engineering, 8+ years relevant experience, RTL/Verilog, FPGA transceiver and timing experience, C/C++, EM/FPGA tool flow familiarity, lab equipment experience.
C, C++, Linux, Windows, Verilog HDL, Intel FPGA tool flows, Xilinx FPGA tool flows, UVM, ATE
2w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
3mo
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Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
2w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
3mo
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Senior Staff FPGA/FW/SW Verification Engineer -Platform development for on-board subsystems
Santa Clara, California, United States
$128k-$191k/yr OnsiteFull Time
5+ YOEBachelor in Computer Engineering; 5+ years data communication; HW/FW/SW mix; Verilog, C/C++, Python; SystemVerilog; lab equipment; strong cross-functional communication.
Verilog, SystemVerilog, Python, C/C++, Tcl, Perl
1mo
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Senior Electrical Engineer
Santa Clara, California, United States
$150k-$190k/yr OnsiteFull Time
5+ YOE5+ years electrical engineering experience, PCB and mixed-signal design, FPGA bring-up (Verilog/SystemVerilog), embedded Linux familiarity, experience with Altium or Mentor Graphics, and bachelor’s in electrical engineering.
Altium Designer, Mentor Graphics, Verilog, SystemVerilog, Yocto, Bitbake, Embedded Linux, I2C, SPI, UART, USB, DP, HDMI, MIPI, Camera Link, CoaXPress, NXP i.MX, Qualcomm, Kinetis, DDR, FLASH, FPGA, oscilloscopes, logic analyzers
2mo
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Principal Hardware Engineer
Sunnyvale, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOEBS or MS in Electrical/Computer Engineering; 10+ years board/FPGA design; Verilog; Unix/Linux; 2+ days in Sunnyvale; US citizen or Green Card; does not sponsor visa.
Verilog, PCIe, Ethernet, I2C, Linux, Unix, FPGA, VHDL, Schematic Capture, Lab Equipment
2mo
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SoC Design Engineer
Santa Clara, California, United States
$111k-$140k/yr OnsiteFull Time
PhD or MS in Electrical Engineering with digital design experience; Verilog RTL, synthesis, STA, and formal verification; FPGA/emulation knowledge; SOC architecture; image processing DSP a plus.
Verilog, RTL, Synthesis, Static Timing Analysis, Formality, FPGA, Emulation, Image Processing DSP
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Sr Staff Engineer Instrument Architecture
Milpitas, California, United States
$169k-$270k/yr HybridFull Time
12+ YOEBachelor’s in engineering,12+ years systems engineering experience, expertise in real-time control, data pipeline and FPGA processing, optics and fluidics knowledge, regulated design control experience.
RTOS, FPGA, DMA, PCIe, USB 3.0, Gigabit Ethernet, RS232, USB, TCP/IP, CAN bus, SPI, I2C
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