580 design verification jobs at 146 companies in California
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
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Design Verification Architect
San Jose or United States
$150k-$300k/yr HybridFull Time
12+ YOEBachelor's/Master's in EE/CE, 12+ years design verification experience for large SoCs, expertise in SystemVerilog, UVM, Portable Stimulus (PSS), coverage-driven and assertion-based verification, and strong architecture and debugging skills.
SystemVerilog, UVM, Portable Stimulus (PSS), PCIe, DDR, Ethernet, CXL, UCIe
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Director, Design Verification
Santa Clara, California, United States
$195k-$292k/yr OnsiteFull Time
10+ YOE10+ years SOC/design verification experience; strong verification methodology, testbench development, scripting (Perl, Python, Tcl, UNIX Shell); ASIC/SoC tape-out experience; excellent communication and cross-functional leadership.
Perl, Python, Tcl, UNIX Shell
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Design Verification Lead
San Jose, California, United States
$200k-$300k/yr HybridFull Time
10+ YOEMinimum 10 years UVM design verification experience; Bachelor's or Master's in EE/CE/CS or related; expertise in SystemVerilog/Verilog, UVM, high-speed protocol verification (PCIe, CXL, Ethernet); scripting with Python/Perl; technical leadership and mentoring.
UVM, SystemVerilog, Verilog, PCIe, CXL, Ethernet, Python, Perl, HLS
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Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification, emulation platforms, SoC verification strategy and leadership.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, Artificial Intelligence, Machine Learning, PCIe, CXL, HBM3, NVLink
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GSoC Design Verification Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree required; experience with SystemVerilog, UVM, C, SVA, coverage-driven verification, SoC design, Python or scripting, and AI-assisted verification workflows.
SystemVerilog, UVM, C, Python, SVA, Portable Stimulus (PSS), Veloce, Palladium, ZeBu, GPT, Claude, Llama
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog/UVM, formal verification, emulation experience, BS in EE/CS/CE or related.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification and emulation experience, bachelor\u0002s in EE/CS or related.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce
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Design Verification Intern
Burlingame, California, United States
$45-$60/hr OnsiteInternship, Temporary
Pursuing a computer science, electrical engineering, or related degree; familiarity with CPU/GPU verification; proficiency in SystemVerilog, SystemC, or C/C++; UVM is a plus; strong debugging and communication skills.
SystemVerilog, SystemC, C++, UVM, Python, LLMs
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Senior Design Verification Engineer
Mountain View or Redmond or Hillsboro
$120k-$235k/yr HybridFull Time
Experience creating verification environments, pre-/post-silicon validation, strong knowledge of verification methodologies and languages, and ability to pass security/export screenings.
Verilog, VHDL, System Verilog, UVM, C/C++, Python, Ruby, Perl, Makefiles, FPGA
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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