393 design verification engineer jobs at 97 companies in Albany, CA
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
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Design Verification Engineer
San Jose, California, United States
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in computer science, computer engineering, or related field; 5+ years' relevant experience; strong SystemVerilog and UVM proficiency; digital design, SoC architecture, verification, scripting, and simulation debugging expertise.
SystemVerilog, UVM, Python, Perl, TCL, shell scripting, Claude
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Design Verification Engineer
Mountain View or California or United States or New York
$102k-$202k/yr HybridFull Time
1+ YOEMaster’s degree and 1+ year, or bachelor’s degree and 2+ years, in engineering or computer science; experience with pre-silicon verification, SystemVerilog, UVM, formal verification, and scripting.
SystemVerilog, UVM, SVA, C, C++, Python, Ruby, Perl, Assembly, Makefiles
2mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
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Staff Design Verification Engineer
Sunnyvale, California, United States
$250k-$300k/yr OnsiteFull Time
10+ YOERequires 10+ years of design verification experience, SystemVerilog, DPI, UVM, Python or Perl, scalable testbench development, verification tools, and strong debugging skills. BS or MS in computer science or electrical engineering desired.
SystemVerilog, DPI, UVM, Python, Perl
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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ASIC Design Verification Engineer
Santa Clara, California, United States
$107k-$161k/yr OnsiteFull Time
0.5+ YOEBachelor's degree in science or engineering; experience with architecture/design tools, scripting/programming, and design verification methods preferred; works under supervision and communicates technical information.
RTL to GDS Flow, Virtuoso
2mo
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEDevelop and execute verification plans using SystemVerilog/UVM and emulation platforms; 5+ years verification experience; bachelor\u0002s in EE/CE/CS; strong debugging, scripting, and coverage skills.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
1mo
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOE5+ years verification experience, Bachelor in EE/CE/CS, strong SystemVerilog/UVM skills, emulation platform experience, scripting (Python/Perl/TCL), debug and coverage-driven verification expertise.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, UPF, CPF, FPGA
3mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
2mo
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Design Verification Engineer, Principal
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
5+ YOEBS in CE/EE/CS with 10+ years (or MS/PhD with 5+ years) verification and firmware/software experience; expertise in System Verilog, UVM, random verification, Python/Perl, EDA tools, OOD, Linux, C++ and ARM assembly; leadership and tape-out experience.
System Verilog, UVM, Python, Perl, EDA Verification tools, Linux, C++, ARM assembly
3mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
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Design Verification Engineer- CPU
Santa Clara, California, United States
$200k-$350k/yr OnsiteFull Time
8+ YOE8+ years verifying high-performance CPUs or complex digital designs; SystemVerilog, UVM, C, C++, assertions, coverage, testbench, and debugging experience; BS+ in engineering or computer science.
SystemVerilog, UVM, C, C++, ARM, RISC-V, FPGA
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Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS/CompE,1+ years design verification experience, SystemVerilog/UVM, Python/MATLAB scripting, testbench and coverage development, RTL and pre/post-silicon validation experience.
SystemVerilog, UVM, Python, MATLAB
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