58 design verification engineer jobs at 17 companies in Benbrook, TX
2mo
Save
Mark Applied
Hide
Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
3mo
Save
Mark Applied
Hide
Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
2mo
Save
Mark Applied
Hide
Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification experience (incl. 5+ years digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and ability to define verification strategy.
Verilog, FastSpice
5d
Save
Mark Applied
Hide
Mixed Signal Design Verification (MSDV) Engineer
Dallas, Texas, United States
OnsiteFull Time
Bachelor's, master's, or PhD in electrical engineering or related field; analog, digital, and mixed-signal verification experience; Verilog, SystemVerilog, UVM, scripting, EDA tools, and strong analytical skills.
Cadence Virtuoso, Verilog, Verilog-A, SystemVerilog, Universal Verification Methodology (UVM), Unix shell, TCL, Perl, Python, SKILL, I2C, PMBus, SPI, DesignSync, SVN, Git
1mo
Save
Mark Applied
Hide
RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
3w
Save
Mark Applied
Hide
SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE or related, 0-2 years digital verification experience, Verilog/SystemVerilog, Python/Tcl/Perl, UNIX/EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, UNIX, EDA design tools, RISC-V, ARM, MIPS, C, C++
3w
Save
Mark Applied
Hide
SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE,0-2 years digital verification experience, proficiency with Verilog/SystemVerilog, scripting (Python,Tcl/Tk,Perl), UNIX and EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, C, C++, UNIX, EDA design tools
1mo
Save
Mark Applied
Hide
Sr. Mixed Signal Design Verification Manager
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, team management experience, hands-on UVM and mixed-signal verification, Spice/Spectre and simulator expertise, strong problem-solving and communication skills.
UVM, VerilogAMS, RNM, Spice/Spectre, Python, shell, SV Assertions, SV-UDN/EENET
4w
Save
Mark Applied
Hide
Design Engineer / Checker - Level 3
Fort Worth, Texas, United States
$82k-$144k/yr OnsiteFull Time
3+ YOEBachelor's in engineering (or equivalent), US citizenship with ability to obtain Secret clearance, 3+ years design/checking CAD experience, Siemens NX proficiency, GD&T knowledge, model‑centric verification, and MS Office skills.
Siemens NX, Siemens TeamCenter, Microsoft Word, Microsoft Excel, Microsoft PowerPoint
2w
Save
Mark Applied
Hide
Staff Engineer, FPGA Design (R5347)
Dallas, Texas, United States
$150k-$230k/yr OnsiteFull Time
Strong FPGA design, implementation, verification skills using VHDL/SystemVerilog; experience with timing closure, clock domain crossing, and high-performance digital communications; degree in STEM; Git proficiency.
VHDL, SystemVerilog, AMD/Xilinx development tools, Vivado, Git, TCL, AXI4, AXI-Stream, CI/CD
1mo
Save
Mark Applied
Hide
Verification and Validation Engineer - Production Line (Dallas, TX, US)
Dallas or Fort Worth or Logan
$69k-$138k/yr OnsiteFull Time
4+ YOEBachelor's in engineering or equivalent experience; minimum 4 years V&V testing of mechatronic/electro-mechanical systems; test design, bug tracking, component integration, mechanical/electrical testing; scripting with Python or Bash; safety analysis experience.
Python, Bash
2mo
Save
Mark Applied
Hide
Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
3w
Save
Mark Applied
Hide
Senior Hardware Engineer
Dallas, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years hardware design experience,analog/digital circuit and embedded systems expertise,FPGA and verification tool experience,hardware testing and compliance knowledge.
Mentor Graphics Expedition xDX Designer, Verilog, ModelSim SE, Altera Quartus II, Quartus Prime, SignalTap II, Xilinx ISE, Vivado, Integrated Logic Analyzer, ChipScope, Lattice Diamond, IBM Rational ClearCase
2mo
Save
Mark Applied
Hide
Staff - Signal Integrity Engineer (Richardson, TX, US)
Richardson, Texas, United States
OnsiteFull Time
6+ YOEPlan digital PCB designs, perform signal integrity simulation and lab verification, troubleshoot high-speed interfaces, lead design reviews, develop schematics/BOMs, and validate systems; strong communication and cross-functional collaboration required.
2mo
Save
Mark Applied
Hide
ICT (In-Circuit-Test) Engineer
Dallas or Houston
$45k-$121k/yr OnsiteFull Time
3+ YOE3+ years VLSI experience; perform VLSI system development, module/IP verification, UVM-based testbench creation, debugging, and client documentation; mandatory VLSI board design skill.
Universal Verification Methodology (UVM), SharePoint, JIRA, Trend Nxt
2w
Save
Mark Applied
Hide
Hardware Designer
Dallas or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelor's in Electrical/Computer Engineering, strong high-speed PCB and system design skills, FPGA familiarity, lab bring-up and verification, Cadence/OrCAD/LTSpice experience.
LTSpice, OrCAD Capture CIS, Cadence Allegro, Verilog, HLS, signal analyzer, oscilloscope, optical test set, signal generator, electronic load, VNA
2w
Save
Mark Applied
Hide
Scientist, Systems Engineering (41785)
Richardson or Plano
OnsiteFull Time
12+ YOELead radar system design, integration, verification and testing; require extensive systems engineering experience and active U.S. secret security clearance.
Microsoft Office, MATLAB, LabView, Python, C/C++, C#
1mo
Save
Mark Applied
Hide
Manager Engineering
Fort Worth, Texas, United States
HybridFull Time
10+ YOEBachelor's or Master's in engineering, 10+ years systems engineering experience, ability to obtain security clearance and be a US Person, experience leading teams, systems-level design/integration/verification, and program cost/schedule management.
Model-Based Systems Engineering
Explore Jobs