225 design verification engineer jobs at 68 companies in Texas
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
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Senior Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS required, 4+ years IP/SoC design or verification experience, Verilog/SystemVerilog/UVM skills, SVA and verification (test planning, simulation, debug), familiarity with Python, C/C++, Perl, TCL and AI/ML tools; ARM AMBA knowledge a plus.
Verilog, SystemVerilog, UVM, System Verilog Assertion (SVA), Python, C/C++, Perl, TCL, Makefiles, AI/ML tools, ARM AMBA, RTL
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Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
3w
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Design Verification Engineer -Staff
Austin, Texas, United States
$154k-$231k/yr OnsiteFull Time
2+ YOEDegree in electrical/computer engineering or computer science and minimum 2 years experience in software/electrical/systems engineering with microprocessor design experience.
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Verify high-throughput cellular baseband modems and transceiver link controllers; strong problem solving and technical aptitude for complex engineering challenges.
3w
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Design Verification Engineer (Silicon Engineering)
Austin, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CS/CE,1+ years design verification experience,SystemVerilog/UVM and testbench development,Python/MATLAB scripting,ability to meet U.S. ITAR eligibility.
SystemVerilog, UVM, Python, MATLAB
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
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Principal Design Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
8+ YOEAdvanced degree or equivalent experience in EE/CE/CS with 3–8+ years technical experience; strong verification, testbench, simulation, and debug skills; ability to pass Microsoft security and export-control screenings.
Verilog, VHDL, C, C++, Python, Ruby, Perl, SystemVerilog, UVM, FPGA
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Sr. Modem Design Verification Engineer
Austin, Texas, United States
$125k-$231k/yr OnsiteFull Time
5+ YOEBSEE/CE required, 5+ years digital design verification experience (modem/PHY preferred), SystemVerilog/UVM, scripting (Python/Perl), strong debugging and verification methodology skills.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Python, Perl, C/C++, MATLAB
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ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
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Design & Verification Engineer, Analog Power Management (7682)
Austin, Texas, United States
$120k-$170k/yr OnsiteMultiple Commitments Available
7+ YOEMSEE with 7+ years in power management design/verification; SIMPLIS experience; PCB design/layout for power; IC design/packaging; strong teamwork; power delivery modeling
SIMPLIS, PCB Design, Power Delivery Modeling
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification experience (incl. 5+ years digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and ability to define verification strategy.
Verilog, FastSpice
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MLA Design Verification Engineer I, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE or related; 1+ years design verification with System Verilog and UVM; 1+ years testbench development (stimulus, checkers, assertions, coverage); EM/FPGA/SoC verification and C/C++ experience preferred.
System Verilog, UVM, FPGA, C/C++
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Digital Design Verification, Principal Engineer-17853
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
12+ YOE12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering.
VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python
1d
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Staff Design Verification Engineer – High Performance CPU Core
Austin or Santa Clara
OnsiteFull Time
7+ YOE7+ years ASIC/CPU/SoC design verification experience, strong SystemVerilog and UVM skills, CPU microarchitecture knowledge, BS in EE/CE/CS, strong debug and verification strategy abilities.
SystemVerilog, UVM, Python, C, C++
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