94 design verification engineer jobs at 34 companies in Brea, CA
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
1d
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
2w
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Design Verification Senior Staff Engineer
Irvine or Santa Clara
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/Computer Engineering, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM and protocol knowledge, scripting (Python/Perl/Shell), debug and coverage skills.
System Verilog, UVM, Python, Perl, Shell, Palladium, Veloce
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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Principal ASIC Design Verification Engineer
United States or Los Angeles
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, strong SystemVerilog/UVM and SVA skills, experience with VCS/Xcelium/Questa and Verdi/SimVision, scripting (Python/Perl/TCL), Git, CI/CD, C/C++, and ITAR U.S. person eligibility.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, C, C++, CI/CD
1mo
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
1mo
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
5+ YOETransistor-level CMOS RF/mixed-signal IC design experience, SPICE and Cadence proficiency, PVT and Monte Carlo verification, degree in electrical engineering (B.S. with 5+ years or advanced degree with reduced experience), strong communication skills.
Cadence Virtuoso, SPICE, spectrum analyzer, oscilloscope, probe station, VNAs
1mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
5+ YOEBachelor's in EE (or related) with 5+ years (masters 3+, PhD 0–2); transistor-level CMOS RF/mixed-signal design experience; SPICE and Cadence proficiency; PVT/Monte Carlo verification; strong communication.
Cadence Virtuoso, SPICE, VNA, spectrum analyzer, oscilloscope, probe station
3w
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
1mo
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
3w
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Design Quality Engineer
Irvine, California, United States
$105k-$135k/yr OnsiteFull Time
5+ YOEBS in technical or life science,5+ years in medical device quality systems (ISO 13485,21 CFR 820),strong technical writing,test planning,verification/validation experience,MS Office proficiency,and ability to travel up to 90 days/yr.
Microsoft Office
2mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
1mo
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Director of Verification & Validation
Huntington Beach, California, United States
$180k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in Biomedical or Mechanical Engineering, 8+ years Class III medical device V&V, knowledge of FDA and IEC/ISO standards, design control expertise, strong technical writing, and experience leading V&V teams.
3w
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Senior Staff Analog and Mixed-Signal IC Design Engineer
Irvine, California, United States
$150k-$221k/yr OnsiteFull Time
3+ YOEDesign mixed-signal CMOS transceiver/SERDES circuits (PLLs, ADCs, regulators, TX/RX, CDRs), perform verification with SPICE/Spectre/MATLAB, lab characterization, and produce design documentation. Bachelor’s degree plus relevant experience required.
SPICE, Spectre, MATLAB, Hsim, Verilog
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