2mo
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Principal Analog Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
10+ YOEMS or PhD in Electrical Engineering; ~10-15+ years in analog/mixed-signal IC design; expertise in high-speed interfaces, PLL/DLL/CDR, SerDes, analog IP integration.
SPICE, layout, simulation, modeling, IP integration, Analog design, Verification
5d
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2mo
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IC Layout Design Engineer
Richardson, Texas, United States
HybridFull Time
3+ YOE3-5 years in RF/Analog/Mixed Signal layout; Cadence Virtuoso/VXL; Calibre; BD/verification; BS in Electrical Engineering; hybrid work arrangement.
Cadence Virtuoso, Cadence VXL, Calibre, PERL, SKILL, PDV
2w
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FPGA Engineer I
McKinney, Texas, United States
$57k-$109k/yr OnsiteFull Time
0+ YOESTEM bachelor’s required typically; less than 2 years relevant experience; FPGA/ASIC design or verification (VHDL/Verilog/SystemVerilog); experience with AMD Vivado, Altera Quartus Prime Pro, or Libero; lab integration and debug; source control and design reviews.
VHDL, Verilog, SystemVerilog, AMD Vivado, Altera Quartus Prime Pro, Libero, UVM, High Level Synthesis (HLS)
5d
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Senior Principal Firmware Engineering Lead
McKinney, Texas, United States
$132k-$252k/yr OnsiteFull Time
10+ YOEActive transferable DoD Secret clearance, U.S. citizenship, STEM degree, ~10+ years FPGA/ASIC firmware experience with VHDL/Verilog, leadership, and system-level FPGA design and verification skills.
Xilinx, Altera, Microsemi, VHDL, Verilog, System Verilog, UVM, Veloce, ARM, Microblaze, Nios, High Level Synthesis (HLS)