23 design verification engineer jobs at 17 companies in Cotati, CA
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
1w
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Intern - Design Verification Infrastructure Engineer - Platform
Santa Clara or Austin or Berkeley or Boston
OnsiteFull Time
Software engineering experience with a compiled and a scripting language, modern engineering practices, production deployments; familiarity with Chisel/CIRCT/MLIR and EDA flows preferred.
Chisel, CIRCT, MLIR, Scala, Python
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Sr. Reliability/Verification Engineer
San Francisco, California, United States
$140k-$200k/yr OnsiteFull Time
8+ YOE8+ years designing and executing reliability and verification strategies for rugged electromechanical and compute systems; FMEA/RCA experience; reliability physics, HALT, thermal and vibration testing; functional safety knowledge preferred.
3w
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Senior Electrical Engineer — Verification & Test
Alameda, California, United States
OnsiteFull Time
5+ YOEBachelor's in electrical engineering,5+ years experience,hands-on lab debugging,verification protocol development,custom test hardware design,Altium and scripting experience,knowledge of FDA design controls/ISO 13485.
Altium Designer, Python, MATLAB, LabVIEW, TestStand, National Instruments, Keithley
4w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
4d
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Software Engineer, Silicon Design Methodology
San Francisco, California, United States
$225k-$380k/yr HybridFull Time
Strong software engineering in C++, Python, Rust, or similar systems languages; experience with engineering infrastructure, developer tools, EDA/CAD, compilers, verification, RTL/IP integration, and digital design.
C++, Python, Rust, EDA, CAD, RTL, IP, SoC
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Staff Electrical Engineer
El Segundo or Los Angeles or Washington or San Francisco or San Diego or Seattle or London
$150k-$210k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering with 8+ years experience in power and analog board design for high-reliability aerospace/defense systems; EMI/EMC, verification, production support, and ability to obtain U.S. security clearance.
6d
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Mechanical Engineer
South San Francisco, California, United States
OnsiteFull Time
5+ YOE5+ years mechanical/electromechanical design experience delivering complex subsystems through NPI to production; strong CAD, FEA, manufacturability, mechanism and actuator design, and verification/test skills.
NX, SolidWorks
3w
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R&D Engineer (Medical Device)
South San Francisco, California, United States
$100k-$120k/yr HybridFull Time
2+ YOEBachelor's in engineering (preferred), 2+ years R&D experience, SolidWorks proficiency, strong documentation and multitasking skills, and ability to support design control and verification testing.
SolidWorks, Microsoft Word, Microsoft Excel, Microsoft PowerPoint
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Sr. Electrical Engineer, Bee
San Francisco, California, United States
$158k-$214k/yr OnsiteFull Time
Experience developing functional specifications, design verification plans, and functional test procedures; PCB and component selection experience; expertise in design validation, compliance testing (FCC/CE), BOM management, and cross-functional product development.
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Manager, Mechanical Design Engineering
Berkeley, California, United States
$192k-$223k/yr OnsiteFull Time
7+ YOE2+ MgmtBachelor’s in Mechanical Engineering,7+ years mechanical design experience,2+ direct reports,FEA and SolidWorks proficiency,DFMA and sheet metal expertise,GD&T (ASME Y14.5-2018),ability to lead verification and production transitions.
SolidWorks, FEA, GD&T (ASME Y14.5-2018)
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Senior Electronic Characterization Engineer (San Francisco, CA, US)
San Francisco, California, United States
$73k-$174k/yr OnsiteFull Time
5+ YOEBachelor’s or Master’s degree in Electrical Engineering; 5+ years in electrical characterization/validation/design verification; ECU testing experience in infotainment/telematics; bench testing and lab instrumentation; experience with automated test environments
Oscilloscopes, Power supplies, Multimeters, Automation frameworks
3w
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Lead Photonics Integrated Circuit Engineer
San Francisco or United States
HybridFull Time
PhD in physics/EE with deep expertise in quantum photonics, semiconductor process integration, PIC design/tape-out, modelling and characterization; experience with Cadence Virtuoso, verification flows and photonic simulation tools.
C++, Python, SKILL, TCL, HDL, MATLAB, Lumerical, COMSOL, MEEP, Cadence Virtuoso, Calibre, Hercules, ICV, Dracula, Primeyield, Verilog-A
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Sr. Staff Firmware Engineer (Embedded OTA & Uptane Security Platform)
Sunnyvale or San Francisco
$189k-$267k/yr OnsiteFull Time
Design and implement embedded OTA/Uptane client frameworks with cryptographic verification; develop safety-critical firmware in C for bare-metal/RTOS and Python host tooling; optimize storage (eMMC, UFS, QSPI) and A/B dual-bank update systems.
Uptane, eMMC, UFS, QSPI, C, Python, RTOS, bootloader
2mo
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Director of Mechanical Engineering, Hardware Platform
Emeryville or Santa Clara
$275k-$320k/yr HybridFull Time
15+ YOE7+ Mgmt15+ years robotics/precision automation; 7+ years leading engineering teams; strong mechanical design, GD&T, DFMEA/PFMEA; prototype-to-production leadership; cross-functional collaboration.
CAD, GD&T, DFMEA, PFMEA, DVP&R, Verification and Validation, Calibration, Testing
4d
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Senior Consultant
San Francisco, California, United States
OnsiteFull Time
5+ YOERequires 5–20 years in hardware-assisted verification, Linux boot and kernel debugging, digital design, emulation, PCIe Gen6, Python, C or Perl scripting, and SystemVerilog RTL coding.
AI, High Performance Computing (HPC), SystemVerilog, Linux, PCIe, HBM, JTAG, UART, Virtual IXIA, ZeBu, Palladium, Veloce, HAPS, Protium, ProFPGA, Python, C, Perl, UVM, C++, SystemC, PCIe Gen6, QEMU
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Member of Technical Staff, Post-Training, RL
San Francisco, California, United States
$350k-$500k/yr OnsiteFull Time
Design and run large-scale post-training experiments for reasoning models; strong research and engineering skills in RL, training dynamics, verification, and infrastructure.
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