81 design verification engineer jobs at 47 companies in Fairfax, CA
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
3d
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Design Verification Engineer
Mountain View or California or United States or New York
$102k-$202k/yr HybridFull Time
1+ YOEMaster’s degree and 1+ year, or bachelor’s degree and 2+ years, in engineering or computer science; experience with pre-silicon verification, SystemVerilog, UVM, formal verification, and scripting.
SystemVerilog, UVM, SVA, C, C++, Python, Ruby, Perl, Assembly, Makefiles
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
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Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS/CompE,1+ years design verification experience, SystemVerilog/UVM, Python/MATLAB scripting, testbench and coverage development, RTL and pre/post-silicon validation experience.
SystemVerilog, UVM, Python, MATLAB
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Design Verification Engineer -Performance Modelling
Mountain View, California, United States
$45k-$121k/yr OnsiteFull Time
5+ YOEBachelor's degree and 5+ years design verification experience with SystemVerilog/UVM, scripting (Python/Perl/Shell), simulator/debug tool experience, strong debugging and KPI-driven performance validation skills.
SystemVerilog, UVM, Python, Perl, Shell, VCS, Xcelium, Questa, Verdi, HVL
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Senior Design Verification Engineer, Silicon
Mountain View, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE/CS or equivalent,8+ years verifying RTL with SystemVerilog,experience with DV testbenches,coverage-driven verification,EMR not applicable.
SystemVerilog, VMM, OVM, UVM, UPF, GLS, Perl, Python
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Sr. FPGA Design & Verification Engineer
San Francisco, California, United States
$137k-$188k/yr HybridFull Time
2+ YOEMaster's degree plus 2+ years or bachelor's degree plus 3+ years of engineering experience; expertise in FPGA and RTL design, VHDL, Verilog, SystemVerilog, simulation, verification, debugging, laboratory equipment, and scripting.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers
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Design Verification Intern
Burlingame, California, United States
$45-$60/hr OnsiteInternship, Temporary
Pursuing a computer science, electrical engineering, or related degree; familiarity with CPU/GPU verification; proficiency in SystemVerilog, SystemC, or C/C++; UVM is a plus; strong debugging and communication skills.
SystemVerilog, SystemC, C++, UVM, Python, LLMs
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ASIC Design Verification Engineer
Mountain View, California, United States
$175k-$215k/yr HybridFull Time
3+ YOE3+ years experience with UVM/SystemVerilog, constrained-random, functional coverage, SVA; strong RTL debug skills; Python proficiency; excellent communication and analytical abilities.
UVM, SystemVerilog, SVA, Python, C, C++, UPF, PCIe Gen 5, PCIe Gen 6, DDR5, Ethernet, LLMs
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI
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Intern - Design Verification Infrastructure Engineer - Platform
Santa Clara or Austin or Berkeley or Boston
OnsiteFull Time
Software engineering experience with a compiled and a scripting language, modern engineering practices, production deployments; familiarity with Chisel/CIRCT/MLIR and EDA flows preferred.
Chisel, CIRCT, MLIR, Scala, Python
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Sr. FPGA Design & Verification Engineer
San Francisco or Oakland
$137k-$188k/yr HybridFull Time
2+ YOERequires a master's degree plus 2+ years, bachelor's degree plus 3+ years, or equivalent experience; FPGA/RTL design, VHDL, Verilog, SystemVerilog, simulation, debugging, scripting, and laboratory equipment experience.
VHDL, Verilog, SystemVerilog, Questa, ModelSim, Python, Tcl, MATLAB, shell scripting, oscilloscopes, logic analyzers, FPGA
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Sr. Reliability/Verification Engineer
San Francisco, California, United States
$140k-$200k/yr OnsiteFull Time
8+ YOE8+ years designing and executing reliability and verification strategies for rugged electromechanical and compute systems; FMEA/RCA experience; reliability physics, HALT, thermal and vibration testing; functional safety knowledge preferred.
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Sr. FPGA Verification Engineer
Mountain View, California, United States
$215k-$300k/yr OnsiteFull Time
8+ YOEBachelor’s degree in electrical or computer engineering, 8+ years of electronics hardware development, FPGA digital logic design, industry-standard design, simulation and synthesis tools, and strong problem-solving skills.
FPGA, DO-254
4w
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Mechanical Design Engineer - Sr. Mechanical Design Engineer
San Carlos, California, United States
$111k-$162k/yr OnsiteFull Time
2+ YOEBachelor's in Mechanical Engineering; 2+ years (engineer) or 8+ years (senior) power transformer design experience; mechanical design focus, CAD proficiency, design verification skills, and ability to relocate to plant commute.
Engineering Automation Platform (EAP), Autodesk Inventor, ERP
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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Senior Electrical Design Engineer
Menlo Park, California, United States
$160k-$240k/yr OnsiteFull Time
4+ YOETechnical degree in electrical engineering, 4+ years electrical design experience, ECAD (Altium/Cadence), PCB layout, component selection, subsystem prototyping, verification, and supply-chain/CM experience.
ECAD, Altium Designer, Cadence, I2C, SPI, USB, MIPI
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Senior Electrical Engineer — Verification & Test
Alameda, California, United States
OnsiteFull Time
5+ YOEBachelor's in electrical engineering,5+ years experience,hands-on lab debugging,verification protocol development,custom test hardware design,Altium and scripting experience,knowledge of FDA design controls/ISO 13485.
Altium Designer, Python, MATLAB, LabVIEW, TestStand, National Instruments, Keithley
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