19 design verification engineer jobs at 6 companies in Folsom, CA
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Design Verification Engineer
Santa Clara or Folsom or Austin
$153k-$229k/yr HybridFull Time
8+ YOEAdvanced SystemVerilog, UVM, C/C++, Python or Perl, and formal verification experience; bachelor's plus 8 years or master's plus 6 years in a related discipline preferred.
SystemVerilog, UVM, C, C++, Python, Perl, DFI, DDR5, LPDDR5, LPDDR6, DIMM, RTL, BIOS, GLS, NLP, XPROP, VIP, BFM
3w
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Senior SoC Design Verification Engineer
Folsom or Santa Clara
$164k-$269k/yr HybridFull Time
8+ YOE8+ years SoC verification experience, bachelor’s in EE/CE/CS, SystemVerilog/OVM/UVM expertise, debugging in pre-silicon, scripting with Python, strong communication and technical leadership.
System Verilog, OVM, UVM, Python
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOESenior verification engineer with 10+ years in VLSI design/verification; strong Verilog/SystemVerilog, UVM; scripting (Python, Perl, TCL); C/C++; leadership.
Verilog, SystemVerilog, UVM, Python, PERL, TCL, C, C++, Specman
2w
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Design Verification Architect
Folsom, California, United States
$164k-$232k/yr HybridFull Time
8+ YOE8+ years pre-silicon IP/SoC validation experience, SystemVerilog and UVM expertise, familiarity with VCS/Verdi, IP environment tools, strong debugging and collaboration skills.
SystemVerilog, VCS, Verdi, UVM, VSCode, GitHub Copilot, Git, Formal Property Verification
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; Verilog/SystemVerilog; UVM; Python, TCL, PERL or similar; C/C++; Bachelor’s or Master’s in Electrical or Computer Engineering.
Verilog, SystemVerilog, UVM, Python, C, C++, Specman, TCL, PERL
2mo
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Senior ASIC verification engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOEBachelor's degree in EE/CE, 10+ years VLSI design/verification experience, proficiency in Verilog/SystemVerilog, UVM, scripting (Python, Perl, Tcl), C/C++, strong VLSI architecture and leadership skills.
Python, Perl, Tcl, C, C++, Verilog, SystemVerilog, UVM, Specman, Electronic Design Automation (EDA), FPGA tools
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; FPGA/EDA; Verilog/SystemVerilog; scripting (Python, TCL, PERL); C/C++; UVM; BS or MS in EE/CS.
Verilog, SystemVerilog, UVM, EDA, C, C++, Python, Perl, TCL
1w
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Principal Engineer - Design
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years experience in SoC design/verification, BS/MS in Electrical/Computer Engineering, experience with serial protocols (SAS/SATA/NVMe, PCIe), Linux and C/Python scripting, RTL (VHDL/Verilog/System Verilog).
Cadence Palladium, Protium, Linux, C, Python, Tcl, Bash, VHDL, Verilog, System Verilog, JTAG, I2C
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
3mo
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Principal Systems Design Engineer
Folsom, California, United States
$175k-$300k/yr OnsiteFull Time
10+ YOEBachelor's in electrical or computer engineering with 10+ years of experience; strong hardware/software systems design, verification, and leadership skills.
3mo
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Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOE5+ years in ASIC/SoC design with Verilog/SystemVerilog, RTL, timing closure, verification; strong problem-solving and communications.
Verilog, SystemVerilog, EDA tools, Synthesis, SVA, Python, Perl
2w
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HBM SoC Physical Design Engineer
Folsom, California, United States
$121k-$205k/yr OnsiteFull Time
3+ YOE3+ years implementing SoC physical design from netlist to GDSII, STA and signoff experience, proficiency with industry EDA tools, knowledge of power intent and verification concepts.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, GDSII, Agentic AI
1mo
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
3mo
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Staff HBM Design Architect - DFT
Richardson or Folsom
$146k-$297k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CE, 5+ years DFT/DFT verification experience in DRAM or ASIC, strong knowledge of scan, MBIST, JTAG and boundary scan, wafer probe/final test experience.
DFT, MBIST, JTAG, boundary scan, TSV
2mo
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Post-silicon Validation and Debug Engineer
Hillsboro or Folsom
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor's degree in EE/CE/CS, 2+ years post-silicon validation/pre-silicon verification or design experience, 1+ year with silicon validation lab equipment and scripting (Python, C/C++, Perl); strong debugging, communication, and cross-functional collaboration skills.
Python, C/C++, Perl, Logic analyzer, Oscilloscope
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