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21 design verification engineer jobs at 6 companies in Davis, CA

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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
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Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
6+ YOEBachelor's in Electrical or Computer Engineering; 6–12 years DV experience using UVM/SystemVerilog; builds DV environments; strong coverage and debugging skills; experience with I2C/SPI/APB/AHB interfaces.
UVM, SystemVerilog, JasperGold, VC Formal, PRBS, eye monitor
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1mo
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IP Design Verification Engineer
Phoenix or Chandler or Hillsboro or Folsom or Santa Clara
$142k-$200k/yr OnsiteFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEDegree in EE/CE (or related) with relevant years of experience; 3+ years in SystemVerilog/Verilog and UVM/OVM; experience with Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa; analog behavioral modeling and PCIe/UCIe experience.
System Verilog, Verilog, UVM, OVM, Synopsys VCS, Cadence Xcelium, JasperGold, Mentor Questa, PCIe, UCIe
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
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Principal Systems Design Engineer
Folsom, California, United States
$175k-$300k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
10+ YOEBachelor's in electrical or computer engineering with 10+ years of experience; strong hardware/software systems design, verification, and leadership skills.
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
Samsung Semiconductor
Samsung SemiconductorKorea Exchange: 005930: Designs and manufactures memory chips, processors, and sensors.
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
Solidigm
Solidigm: Develops and manufactures NAND flash memory and solid-state drives.
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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