31 design verification engineer jobs at 17 companies in Highland, CA
3w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
1w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
21h
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RFIC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced understanding of RFIC design, simulation, layout, and verification; deep submicron process experience; industrial experience; and a Ph.D. or Master of Science in Electrical Engineering.
1mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
1mo
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
1mo
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
2mo
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
1mo
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Design Quality Engineer
Irvine, California, United States
$105k-$135k/yr OnsiteFull Time
5+ YOEBS in technical or life science,5+ years in medical device quality systems (ISO 13485,21 CFR 820),strong technical writing,test planning,verification/validation experience,MS Office proficiency,and ability to travel up to 90 days/yr.
Microsoft Office
2mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
1w
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Sr. Engineer, Quality
Irvine, California, United States
$106k-$169k/yr OnsiteFull Time
1+ YOEDegree in engineering or scientific field with relevant experience; hands-on design assurance, design controls, risk management, verification/validation, statistical techniques, and regulated industry experience required.
Six Sigma, Lean
1w
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Senior Test Engineer
Orange, California, United States
$113k-$137k/yr HybridFull Time
7+ YOEBachelor's in engineering,7+ years product test/verification experience,hands-on test fixture and automation design,data acquisition and analysis,root-cause troubleshooting,strong communication and cross-functional collaboration.
Dewesoft, LabVIEW, SolidWorks
2mo
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Staff Engineer, R&D
Aliso Viejo, California, United States
$117k-$123k/yr OnsiteFull Time
6+ YOEBachelor's in engineering or scientific field, 6+ years medical device experience, SolidWorks expertise, strong mechanical engineering fundamentals, EMR not applicable, proficiency with Microsoft Office, test method and design verification experience.
SolidWorks, Microsoft Word, Microsoft Excel, Microsoft Outlook, Microsoft Teams
1mo
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Staff R&D Engineer- NPD (Onsite Irvine, CA)
Irvine, California, United States
$103k-$171k/yr OnsiteFull Time
4+ YOEBachelor's in Mechanical/Biomedical engineering, 4+ years relevant engineering experience, medical device/regulatory experience preferred, SolidWorks and GD&T experience, proficiency with Microsoft Office, design verification/validation and quality system knowledge.
SolidWorks, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, MS Project, Minitab
1mo
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Systems V&V Engineer
Santa Clara or Irvine
$80k-$90k/yr OnsiteFull Time
2+ YOE2+ years design verification for medical devices, statistical analysis skills, leadership experience, familiarity with IEC 60601-1 and IEC 62304, ability to develop/validate test methods and investigate anomalies.
IEC 60601-1, IEC 62304, Electronic Medical Records (EMR)
1mo
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Lead, RF/Wireless Engrg (39397)
Yorba Linda, California, United States
$128k-$237k/yr OnsiteFull Time
9+ YOERequires extensive RF and embedded hardware experience, ability to define architecture, lead design and verification, FPGA and PCB tool experience, ability to obtain Secret clearance, and 7–9+ years of related experience depending on degree.
Altium, Mentor Graphics, MATLAB, Simulink, P-Spice, Agilent ADS, AWR, Ansys HFSS, Xilinx ISE, Xilinx EDK, ModelSim, MS Office
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