61 design verification engineer jobs at 20 companies in Mansfield, TX
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
1mo
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
3mo
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
2mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification experience (incl. 5+ years digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and ability to define verification strategy.
Verilog, FastSpice
1w
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Mixed Signal Design Verification (MSDV) Engineer
Dallas, Texas, United States
OnsiteFull Time
Bachelor's, master's, or PhD in electrical engineering or related field; analog, digital, and mixed-signal verification experience; Verilog, SystemVerilog, UVM, scripting, EDA tools, and strong analytical skills.
Cadence Virtuoso, Verilog, Verilog-A, SystemVerilog, Universal Verification Methodology (UVM), Unix shell, TCL, Perl, Python, SKILL, I2C, PMBus, SPI, DesignSync, SVN, Git
1mo
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
3w
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE or related, 0-2 years digital verification experience, Verilog/SystemVerilog, Python/Tcl/Perl, UNIX/EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, UNIX, EDA design tools, RISC-V, ARM, MIPS, C, C++
3w
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SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE,0-2 years digital verification experience, proficiency with Verilog/SystemVerilog, scripting (Python,Tcl/Tk,Perl), UNIX and EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, C, C++, UNIX, EDA design tools
1mo
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Sr. Mixed Signal Design Verification Manager
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, team management experience, hands-on UVM and mixed-signal verification, Spice/Spectre and simulator expertise, strong problem-solving and communication skills.
UVM, VerilogAMS, RNM, Spice/Spectre, Python, shell, SV Assertions, SV-UDN/EENET
1mo
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Design Engineer / Checker - Level 3
Fort Worth, Texas, United States
$82k-$144k/yr OnsiteFull Time
3+ YOEBachelor's in engineering (or equivalent), US citizenship with ability to obtain Secret clearance, 3+ years design/checking CAD experience, Siemens NX proficiency, GD&T knowledge, model‑centric verification, and MS Office skills.
Siemens NX, Siemens TeamCenter, Microsoft Word, Microsoft Excel, Microsoft PowerPoint
3w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2w
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Staff Engineer, FPGA Design (R5347)
Dallas, Texas, United States
$150k-$230k/yr OnsiteFull Time
Strong FPGA design, implementation, verification skills using VHDL/SystemVerilog; experience with timing closure, clock domain crossing, and high-performance digital communications; degree in STEM; Git proficiency.
VHDL, SystemVerilog, AMD/Xilinx development tools, Vivado, Git, TCL, AXI4, AXI-Stream, CI/CD
1mo
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Verification and Validation Engineer - Production Line (Dallas, TX, US)
Dallas or Fort Worth or Logan
$69k-$138k/yr OnsiteFull Time
4+ YOEBachelor's in engineering or equivalent experience; minimum 4 years V&V testing of mechatronic/electro-mechanical systems; test design, bug tracking, component integration, mechanical/electrical testing; scripting with Python or Bash; safety analysis experience.
Python, Bash
2mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
4d
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Senior Electrical Engineer
Plano, Texas, United States
$78k-$156k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related engineering discipline and at least 5 years of electrical or electronic engineering experience. Requires circuit design, PCB development, verification, and regulated product experience.
C#, Python, PCB
4d
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Senior Electrical Engineer
Plano, Texas, United States
$78k-$156k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related engineering discipline and 5+ years of electrical/electronic engineering experience. Requires circuit design, PCB development, verification testing, and regulated product experience.
C#, Python, PCB
3w
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Senior Hardware Engineer
Dallas, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years hardware design experience,analog/digital circuit and embedded systems expertise,FPGA and verification tool experience,hardware testing and compliance knowledge.
Mentor Graphics Expedition xDX Designer, Verilog, ModelSim SE, Altera Quartus II, Quartus Prime, SignalTap II, Xilinx ISE, Vivado, Integrated Logic Analyzer, ChipScope, Lattice Diamond, IBM Rational ClearCase
2d
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FPGA Engineer II
Plano, Texas, United States
$69k-$131k/yr OnsiteFull Time
2+ YOESTEM degree and 2+ years relevant experience, with FPGA/ASIC design or verification, vendor devices and tools, lab integration, Git, Python or C, CI/CD, and digital simulation experience.
AMD, Altera, Microchip, AMD Vivado, Altera Quartus Prime Pro, Libero, VHDL, Verilog, SystemVerilog, Git, Python, C, CI/CD, Questa, RivieraPro, ARM, Microblaze, NIOS, UVM, High Level Synthesis (HLS), GPUs, AES, RSA, ECC
2mo
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Staff - Signal Integrity Engineer (Richardson, TX, US)
Richardson, Texas, United States
OnsiteFull Time
6+ YOEPlan digital PCB designs, perform signal integrity simulation and lab verification, troubleshoot high-speed interfaces, lead design reviews, develop schematics/BOMs, and validate systems; strong communication and cross-functional collaboration required.
2mo
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ICT (In-Circuit-Test) Engineer
Dallas or Houston
$45k-$121k/yr OnsiteFull Time
3+ YOE3+ years VLSI experience; perform VLSI system development, module/IP verification, UVM-based testbench creation, debugging, and client documentation; mandatory VLSI board design skill.
Universal Verification Methodology (UVM), SharePoint, JIRA, Trend Nxt
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