344 design verification engineer jobs at 64 companies in Marina, CA
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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SoC Design Verification Engineer
Santa Clara, California, United States
$106k-$173k/yr OnsiteFull Time
1+ YOEBachelor's degree with 1+ year related experience, or master's/PhD in electrical, computer science, engineering, or related field; experience in SoC design validation or verification and verification methodologies.
UVM, SystemVerilog, OVM, VM, Xeon, scripting languages
1mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
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Staff Design Verification Engineer
Sunnyvale, California, United States
$250k-$300k/yr OnsiteFull Time
10+ YOERequires 10+ years of design verification experience, SystemVerilog, DPI, UVM, Python or Perl, scalable testbench development, verification tools, and strong debugging skills. BS or MS in computer science or electrical engineering desired.
SystemVerilog, DPI, UVM, Python, Perl
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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C - Focused Design Verification Engineer
Sunnyvale, California, United States
OnsiteFull Time
Experience in design verification for wireless systems-on-chip, including RTL, emulation, and verification methodologies.
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ASIC Design Verification Engineer
Santa Clara, California, United States
$107k-$161k/yr OnsiteFull Time
0.5+ YOEBachelor's degree in science or engineering; experience with architecture/design tools, scripting/programming, and design verification methods preferred; works under supervision and communicates technical information.
RTL to GDS Flow, Virtuoso
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
2mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEDevelop and execute verification plans using SystemVerilog/UVM and emulation platforms; 5+ years verification experience; bachelor\u0002s in EE/CE/CS; strong debugging, scripting, and coverage skills.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOE5+ years verification experience, Bachelor in EE/CE/CS, strong SystemVerilog/UVM skills, emulation platform experience, scripting (Python/Perl/TCL), debug and coverage-driven verification expertise.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, UPF, CPF, FPGA
2mo
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Design Verification Engineer, Principal
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
5+ YOEBS in CE/EE/CS with 10+ years (or MS/PhD with 5+ years) verification and firmware/software experience; expertise in System Verilog, UVM, random verification, Python/Perl, EDA tools, OOD, Linux, C++ and ARM assembly; leadership and tape-out experience.
System Verilog, UVM, Python, Perl, EDA Verification tools, Linux, C++, ARM assembly
3mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
3w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years verification experience,proficient in SystemVerilog and UVM,experience with emulation platforms (Palladium/ZeBu/Veloce),debugging,and scripting (Python/Perl/TCL).
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, FPGA
2mo
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
1mo
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Sr. Design Verification Engineer
San Jose, California, United States
$130k-$160k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE, 7+ years RTL/functional verification using SV/UVM, PCIe and gate-level experience, firmware-based simulation and C knowledge, strong debugging and scripting (Python/Perl/Shell) skills.
SV, UVM, C, Python, Perl, Shell scripting, PILOT
2mo
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ASIC Design Verification Engineer, Google Cloud
Sunnyvale, California, United States
$117k-$166k/yr OnsiteFull Time
1+ YOEBachelor's in Electrical/Computer Engineering or CS; 1 year design verification; SystemVerilog/Verilog experience.
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
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