77 design verification engineer jobs at 29 companies in Shadow Hills, CA
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
3mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
1w
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Staff Design Verification Test Engineer
Costa Mesa, California, United States
$191k-$253k/yr OnsiteFull Time
12+ YOEBachelor's degree in engineering, physics, or related field; 12+ years in test, verification, or product engineering; RF/microwave measurement, DVT, NPI, failure triage, and engineering leadership experience.
Lattice OS, spectrum analyzers, signal analyzers, VNAs, signal generators, power meters
2mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
1mo
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Principal ASIC Design Verification Engineer
United States or Los Angeles
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, strong SystemVerilog/UVM and SVA skills, experience with VCS/Xcelium/Questa and Verdi/SimVision, scripting (Python/Perl/TCL), Git, CI/CD, C/C++, and ITAR U.S. person eligibility.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, C, C++, CI/CD
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
2d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree and 2+ years of ASIC, FPGA, or SoC verification experience, or master's with related coursework. Requires digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain Secret clearance.
SystemVerilog, UVM, UVC
2d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent in a related technical field, 2+ years of relevant verification experience or related master's coursework, digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain a Secret clearance.
SystemVerilog, UVM
1w
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RFIC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced understanding of RFIC design, simulation, layout, and verification; deep submicron process experience; industrial experience; and a Ph.D. or Master of Science in Electrical Engineering.
5d
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Principal Analog Design Engineer
Irvine or San Jose or Vancouver or Ottawa
$150k-$250k/yr OnsiteFull Time
5+ YOEMaster’s or PhD in electrical engineering or a related field, 5+ years of experience, strong analog design fundamentals, and experience with Virtuoso, Spectre, ADE, and advanced CMOS verification flows.
Virtuoso, Spectre, ADE, EMX, Momentum, HFSS, CMOS, FinFET, PLL, VCOs, VGA, CTLE, DRV, LDOs
2mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
1mo
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
5+ YOETransistor-level CMOS RF/mixed-signal IC design experience, SPICE and Cadence proficiency, PVT and Monte Carlo verification, degree in electrical engineering (B.S. with 5+ years or advanced degree with reduced experience), strong communication skills.
Cadence Virtuoso, SPICE, spectrum analyzer, oscilloscope, probe station, VNAs
1mo
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
1mo
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
5+ YOEBachelor's in EE (or related) with 5+ years (masters 3+, PhD 0–2); transistor-level CMOS RF/mixed-signal design experience; SPICE and Cadence proficiency; PVT/Monte Carlo verification; strong communication.
Cadence Virtuoso, SPICE, VNA, spectrum analyzer, oscilloscope, probe station
1mo
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
2mo
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Hardware Verification Engineer (Agoura Hills, CA, US)
Agoura Hills, California, United States
$141k-$226k/yr OnsiteFull Time
Strong experience with schematic capture, PCB layout, hardware bring-up, design and debug of complex high-component-count boards, high-current power and mixed-signal electronics, production/DFM support, and independent end-to-end problem solving.
ATE
1mo
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Director of Verification & Validation
Huntington Beach, California, United States
$180k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in Biomedical or Mechanical Engineering, 8+ years Class III medical device V&V, knowledge of FDA and IEC/ISO standards, design control expertise, strong technical writing, and experience leading V&V teams.
2mo
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Graduate - Analog Mixed-Signal Design Engineer
El Segundo or California
$87k-$109k/yr OnsiteFull Time
0+ YOERecent graduate (within last year). Master's or PhD preferred in electronics or related fields. Proficiency with Cadence mixed-signal tools, experience in data-converter or clock-generation IP design/simulation, strong communication and verification skills.
Cadence mixed-signal design tool suite, AI tools
3w
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Principal Systems Engineer, Aircraft Simulation and Design Integration
Huntington Beach, California, United States
$180k-$250k/yr OnsiteFull Time
Bachelor's in engineering required, significant experience with aircraft-level modeling and simulation, proficiency in MATLAB/Simulink, Python, C/C++, model verification/validation, and strong technical leadership and communication.
MATLAB/Simulink, Python, C/C++, SysML, CFD, finite-element analysis
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