2mo
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
1mo
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
3mo
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
2mo
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Design Engineer Verification (2026 New College Graduate)
Richardson, Texas, United States
$72k-$148k/yr OnsiteFull Time
0+ YOEBachelor’s or Master’s in Electrical/Electronics/Computer Engineering with HDL/verification knowledge; GPA 3.0; Verilog/SystemVerilog; UNIX experience; English fluency; curiosity to learn; internship/leadership preferred.
Verilog, SystemVerilog, UNIX, Assembly, Test Bench, VLSI Design
1mo
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
2mo
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Design Engineer Verification (2026 New College Graduate)
Richardson, Texas, United States
$72k-$148k/yr OnsiteFull Time
Bachelor's or Master's in Electrical/Electronics/Computer Engineering, 3.0+ GPA, knowledge of Verilog/System-Verilog, RISC V architecture, UNIX and assembly, strong communication and documentation skills.
Verilog, System-Verilog, RISCV, UNIX, Assembly
1mo
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Sr. Mixed Signal Design Verification Manager
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, team management experience, hands-on UVM and mixed-signal verification, Spice/Spectre and simulator expertise, strong problem-solving and communication skills.
UVM, VerilogAMS, RNM, Spice/Spectre, Python, shell, SV Assertions, SV-UDN/EENET
1w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
6d
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Staff Engineer, FPGA Design (R5347)
Dallas, Texas, United States
$150k-$230k/yr OnsiteFull Time
Strong FPGA design, implementation, verification skills using VHDL/SystemVerilog; experience with timing closure, clock domain crossing, and high-performance digital communications; degree in STEM; Git proficiency.
VHDL, SystemVerilog, AMD/Xilinx development tools, Vivado, Git, TCL, AXI4, AXI-Stream, CI/CD
1mo
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Verification and Validation Engineer - Production Line (Dallas, TX, US)
Dallas or Fort Worth or Logan
$69k-$138k/yr OnsiteFull Time
4+ YOEBachelor's in engineering or equivalent experience; minimum 4 years V&V testing of mechatronic/electro-mechanical systems; test design, bug tracking, component integration, mechanical/electrical testing; scripting with Python or Bash; safety analysis experience.
Python, Bash
2mo
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale
1mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
2w
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Senior Hardware Engineer
Dallas, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years hardware design experience,analog/digital circuit and embedded systems expertise,FPGA and verification tool experience,hardware testing and compliance knowledge.
Mentor Graphics Expedition xDX Designer, Verilog, ModelSim SE, Altera Quartus II, Quartus Prime, SignalTap II, Xilinx ISE, Vivado, Integrated Logic Analyzer, ChipScope, Lattice Diamond, IBM Rational ClearCase
1mo
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Staff - Signal Integrity Engineer (Richardson, TX, US)
Richardson, Texas, United States
OnsiteFull Time
6+ YOEPlan digital PCB designs, perform signal integrity simulation and lab verification, troubleshoot high-speed interfaces, lead design reviews, develop schematics/BOMs, and validate systems; strong communication and cross-functional collaboration required.
1w
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Primary Quality Engineer NPI LCM
Irving, Texas, United States
OnsiteFull Time
3+ YOEBachelor's in engineering or related field, 3+ years in regulated industry quality engineering, familiarity with GMP/ISO, design control, risk management (FMEA), verification/validation, audits and CAPA.
1w
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Senior Principal Firmware Engineering Lead
McKinney, Texas, United States
$132k-$252k/yr OnsiteFull Time
10+ YOEActive transferable DoD Secret clearance, U.S. citizenship, STEM degree, ~10+ years FPGA/ASIC firmware experience with VHDL/Verilog, leadership, and system-level FPGA design and verification skills.
Xilinx, Altera, Microsemi, VHDL, Verilog, System Verilog, UVM, Veloce, ARM, Microblaze, Nios, High Level Synthesis (HLS)
5d
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Hardware Designer
Dallas or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelor's in Electrical/Computer Engineering, strong high-speed PCB and system design skills, FPGA familiarity, lab bring-up and verification, Cadence/OrCAD/LTSpice experience.
LTSpice, OrCAD Capture CIS, Cadence Allegro, Verilog, HLS, signal analyzer, oscilloscope, optical test set, signal generator, electronic load, VNA
6d
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Scientist, Systems Engineering (41785)
Richardson or Plano
OnsiteFull Time
12+ YOELead radar system design, integration, verification and testing; require extensive systems engineering experience and active U.S. secret security clearance.
Microsoft Office, MATLAB, LabView, Python, C/C++, C#
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