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Digital Design Engineer
Austin or Greensboro or Chandler
HybridFull Time
2+ YOEDegree in Electrical or Computer Engineering; 2+ years digital IC design; Verilog RTL; digital design flow; state machines; CMOS VLSI knowledge; strong problem solving.
Verilog, UVM, MATLAB, Simulink
1d
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering or related, 10+ years digital electronics and PCB design experience, knowledge of high-speed interfaces, lab test equipment, and engineering review processes. U.S. citizenship and ability to obtain clearance required.
Siemens PADS, VHDL, Verilog, Logic Analyzers, Signal Generators, Oscilloscopes, Protocol Analyzers, Spectrum Analyzers, Network Analyzers, USB3.x, Ethernet, PCIe, I2C, SPI
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
10+ YOEBachelor's in EE,10+ years digital electronics design experience, PCB and high-speed digital expertise, proficiency with interfaces/protocols, lab test equipment experience, strong communication skills; U.S. citizenship required.
Siemens PADS, VHDL, Verilog, USB3.x, Ethernet, PCIe, I2C, SPI, Logic Analyzer, Signal Generator, Oscilloscope, Protocol Analyzer, Spectrum Analyzer, Network Analyzer
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Digital Layout Design Engineer
Austin, Texas, United States
OnsiteFull Time
Design custom digital layouts and macros for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
CAD
1mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
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Senior Digital Design Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelors in EE/CE/CS required, 4+ years IP or SoC design experience, expert Verilog, knowledge of SoC architecture, experience with Lint/CDC/STA, ARM AMBA desired; C and scripting (Perl/Python) and functional safety are a plus.
Verilog, System Verilog, Lint, CDC, Static Timing Analysis (STA), ARM AMBA, C, Perl, Python
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
1mo
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Hardware Digital Engineer (PCB Design)
Austin, Texas, United States
HybridFull Time
5+ YOEBachelor's in Electrical, Computer, or Software Engineering; 5+ years digital hardware design; VHDL/SystemVerilog; FPGA; schematic capture; PCB layout; relocation to Austin; US work authorization without sponsorship.
VHDL, SystemVerilog, Schematic Capture, PCB Design Tools, FPGA
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
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Sr. Staff Engineer - Digital Design Verification
Austin, Texas, United States
OnsiteFull Time
8+ YOEBSEE or MSEE with 8+ years verifying complex SoC digital designs using SystemVerilog/UVM and C/C++; proven tape-outs, SoC-level verification, and strong collaboration and debugging skills.
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile
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Digital Design Verification, Principal Engineer-17853
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
12+ YOE12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering.
VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python
1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
1mo
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DFT Design Engineer
Austin, Texas, United States
OnsiteFull Time
2+ YOEUS citizenship required. 2+ years SoC/ASIC digital design experience focused on DFT, including scan chain insertion, compression scan, MBIST/LBIST, ATPG, JTAG/IEEE standards, Verilog testbench debugging, and familiarity with Cadence tools/flows.
Cadence tools and flows, Verilog, ATPG, MBIST, LBIST, JTAG 1149.1/6, IEEE1500, IEEE1687
1mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Computer/Electrical Engineering with relevant experience; strong background in digital synthesis, physical design flows, and verification.
Synopsys, Cadence, Synthesis, Place and Route, Static Timing Analysis, DRC/LVS, TCL scripting
1mo
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VLSI Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years ASIC/VLSI digital design experience; strong Verilog/SystemVerilog; familiarity with simulation and verification methodologies, synthesis/timing analysis, and protocol implementation; BS/MS in EE/CE.
Verilog, SystemVerilog, Python, Perl, TCL, EDA tools, SDC, CDC, Linting, Formal Verification
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Senior IP Design Engineer
Austin or San Diego
$129k-$204k/yr OnsiteFull Time
5+ YOE5+ years RTL design experience, proficiency in SystemVerilog and architectural modeling, knowledge of digital design and sign-off checks (LINT, CDC, CLP), familiarity with SDC/UPF and EDA flows.
SystemVerilog, RTL, LINT, CDC, CLP, SDC, UPF, EDA, Claude
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
2mo
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
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