HiringCafe
Join our community

57 digital verification engineer jobs at 32 companies in San Francisco, CA

1w
Save
Mark Applied
Hide
Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
Neuralink
Neuralink: Developing implantable brain-computer interfaces to restore human capabilities.
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
Job PostingView all
3w
Save
Mark Applied
Hide
Digital Verification Engineer
Santa Clara, California, United States
OnsiteFull Time
Nexthop AI
Nexthop AI: Builds high-performance networking infrastructure for large-scale AI cloud deployments.
3+ YOE3+ years digital verification experience for FPGA/ASIC, proficiency in Verilog/SystemVerilog, experience with Modelsim/Questasim or NC-Verilog, BS/MS in EE/CE, strong coverage and assertion skills.
Verilog, SystemVerilog, Modelsim, Questasim, NC-Verilog, UVM
Job PostingView all
1mo
Save
Mark Applied
Hide
Digital Verification Engineer - Weapon Subsystems 2
Albuquerque or Livermore or United States
$122k-$238k/yr HybridFull Time, Temporary
Sandia National Laboratories
Sandia National Laboratories: Conducts science and engineering research for national security.
Bachelor's in relevant discipline (or equivalent experience), ability to obtain DOE Q-level clearance, expertise in formal verification, VHDL/Verilog/SVA proficiency, strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
Job PostingView all
2mo
Save
Mark Applied
Hide
Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Sandia National Laboratories
Sandia National Laboratories: Federal research and development laboratory for national security.
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
Job PostingView all
1mo
Save
Mark Applied
Hide
Digital Verification Engineer (MTD, San Jose, CA)
San Jose, California, United States
$135k-$217k/yr OnsiteFull Time
Teradyne
TeradyneNASDAQ: TER: Designs and manufactures automated test equipment and advanced robotics systems.
6+ YOEMaster's+6yrs or Bachelor's+8yrs in EE/Comp Eng/CS, experience with verification test plans, EDA tools, SystemVerilog/UVM, industry protocols, and source control.
Cadence ePlanner, Cadence Xcelium, Simvision, System Verilog, UVM, AXI, PCIe, DDR3, DDR4, DDR5, clearcase, git, svn, Make, TCL, Perl, Python
Job PostingView all
1mo
Save
Mark Applied
Hide
Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
Job PostingView all
1mo
Save
Mark Applied
Hide
SoC Digital Verification Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
TikTok
TikTok: Global short-form video hosting and social media platform.
1+ YOEBachelor's in a related field,1+ years ASIC/SoC verification experience,mastery of SystemVerilog and UVM,proficiency with simulation/debug tools and Python/Perl/Shell scripting.
SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl, Shell, Palladium, ZeBu, JasperGold, FPGA, ASIC
Job PostingView all
1w
Save
Mark Applied
Hide
Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
Job PostingView all
3w
Save
Mark Applied
Hide
Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
Bachelor's in EE/CE/CS required; coursework in digital logic and HDLs; familiarity with verification concepts, SystemVerilog/UVM, scripting (Python/Tcl/Perl/Shell); strong analytical and communication skills.
Verilog, VHDL, SystemVerilog, Python, C, C++, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Tcl, Perl, Shell
Job PostingView all
3w
Save
Mark Applied
Hide
Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
Bachelor's in EE/CE/CS, coursework or experience with digital logic, HDLs (Verilog/VHDL/SystemVerilog), verification concepts, scripting (Python/Tcl/Perl/Shell), and strong analytical and communication skills.
Verilog, VHDL, SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Python, Tcl, Perl, Shell
Job PostingView all
3w
Save
Mark Applied
Hide
Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
Bachelor's in EE/CE/CS, coursework or projects in digital logic and HDLs, familiarity with verification concepts, exposure to SystemVerilog and UVM, scripting experience (Python/Tcl/Perl/Shell), strong analytical and communication skills.
Verilog, VHDL, SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Python, Tcl, Perl, Shell
Job PostingView all
6d
Save
Mark Applied
Hide
Sr. FPGA Verification Engineer
Mountain View, California, United States
$215k-$300k/yr OnsiteFull Time
Reliable Robotics
Reliable Robotics: Develops autonomous flight systems for commercial and cargo aviation.
8+ YOEBachelor’s degree in electrical or computer engineering, 8+ years of electronics hardware development, FPGA digital logic design, industry-standard design, simulation and synthesis tools, and strong problem-solving skills.
FPGA, DO-254
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer – Physical AI Compute
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
Velaura AI
Velaura AI: Developing ultra-low-power silicon and IP for AI accelerators.
10+ YOE10+ years verifying complex digital/SoC systems with SystemVerilog/UVM,C/C++, assertions, formal, emulation/FPGA, CDC and low-power verification, debugging and HW/SW co-verification.
SystemVerilog, UVM, C, C++, assertions, formal verification, emulation, FPGA, coverage-driven verification
Job PostingView all
2mo
Save
Mark Applied
Hide
Formal Verification - DV
San Jose, California, United States
OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
5+ YOE5+ years design verification with hands-on formal verification experience; strong SystemVerilog/SVA skills; experience with commercial formal tools; deep digital design and SoC interface knowledge; strong RTL/debug skills.
SystemVerilog, SystemVerilog Assertions, UVM, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
Job PostingView all
1mo
Save
Mark Applied
Hide
Formal Verification Engineer - New College Grad 2026
Santa Clara, California, United States
$100k-$190k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
BS/MS/PhD in CS/CE/EE/Math or equivalent; strong fundamentals in formal verification, digital design, and problem solving; familiarity with Verilog/SystemVerilog and scripting; ability to learn quickly and collaborate.
Verilog, SystemVerilog, Python, Tcl, Perl, C/C++, JasperGold, VC Formal
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior Mixed-Signal Verification Engineer -Power Management ICs
San Jose or United States
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
5+ YOE5+ years mixed-signal verification experience for power management ICs, proficiency in RNM/Verilog-A, SystemVerilog/UVM, AMS co-simulation, MATLAB/Simulink, and analog/digital verification flows.
Verilog-A, SystemVerilog, Cadence Xcelium, Spectre, Synopsys VCS, FineSim, CustomSim, AMS Designer, MATLAB, Simulink, UVM, Cadence Virtuoso, SIMPLIS, PLECS, Python, Perl, Tcl
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Staff Design Verification Engineer – Memory Sub-System
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
5+ YOE5-10 years ASIC/SoC verification; DDR/LPDDR/HBM knowledge; System Verilog/UVM; debugging; digital design fundamentals
SystemVerilog, UVM, DDR4, DDR5, LPDDR4, LPDDR5, HBM2, HBM3, SVA, Python, Palladium, Veloce, waveform_debugging
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
Job PostingView all
1mo
Save
Mark Applied
Hide
ASIC Verification Engineer - New College Grad 2026
Santa Clara, California, United States
$100k-$190k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
0+ YOERecent BS or MS graduate in EE/CE/CS; knowledge of digital design, VLSI, computer architecture; SystemVerilog/Verilog, C++, Perl/Python; exposure to VCS, Verdi, Debussy, GDB; strong debugging and analytical skills.
VCS, Verdi, Debussy, GDB, System Verilog, Verilog, C++, Perl, Python
Job PostingView all
1mo
Save
Mark Applied
Hide
Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
Microchip Technology
Microchip TechnologyNASDAQ: MCHP: Designs and manufactures microcontrollers and mixed-signal semiconductor solutions.
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
Job PostingView all

Explore Jobs

Expand Your Job Search