109 engineer digital design engineering jobs at 62 companies in Anaheim, CA
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Digital Design Engineer – Senior Engineering Specialist
El Segundo, California, United States
$129k-$250k/yr OnsiteFull Time
12+ YOEBachelor's in electrical engineering, 12+ years experience in space digital/mixed-signal hardware, US citizenship and ability to obtain security clearance, experience with space qualification, radiation testing, WCCA, HyperLynx and PSPICE, strong troubleshooting and communication skills.
HyperLynx, PSPICE, VHDL, Verilog, System Verilog
3mo
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Electrical Engineering Digital Design Lead
Irvine or Los Angeles
OnsiteFull Time
5+ YOETechnical degree or equivalent, minimum 5 years industry experience, advanced 3D design and coordination skills, competency with document management and Microsoft Office, strong understanding of engineering/architectural concepts and standards, excellent communication and organization.
BIM, Microsoft Office
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
1d
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Digital Design Engineer, Air Dominance and Strike
Costa Mesa, California, United States
$146k-$194k/yr OnsiteFull Time
2+ YOEBachelor's degree in electrical or computer engineering, 2+ years of FPGA, ASIC, or digital design experience, VHDL/Verilog proficiency, Linux, Git, Tcl/Python, and eligibility for a U.S. Secret clearance.
VHDL, Verilog, SystemVerilog, Linux, Git, Tcl, Python, AMD (Xilinx), Intel/Altera, Lattice, AMD (Xilinx) Vitis, Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, MIL-STD-1553, DO-254, Jira
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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Digital Engineer
El Segundo, California, United States
$87k-$198k/yr OnsiteFull Time
5+ YOE5+ years DoD/system engineering; MBSE with digital tools; secret/TS-SCI clearance; bachelor's in STEM; strong collaboration and leadership for design reviews.
MBSE, Cameo, MagicDraw, SparxEA, DOORS, IBM Rhapsody, MATLAB, STK, ModelCenter, TeamCenter, SysML, DoDAF
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ASIC / FPGA Digital Design Engineer – (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree in a related technical field plus 2+ years of FPGA, ASIC, or SoC digital design experience; HDL development, simulation, debugging, synthesis, digital design fundamentals, and U.S. citizenship required.
ASIC, FPGA, SoC, HDL, RTL
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Systems Engineer - Digital Engineering
El Segundo or Colorado Springs
$90k-$130k/yr OnsiteFull Time
2+ YOESystems Engineer with MBSE experience, 2+ years in digital design, defense/DoD space experience, active SECRET clearance.
SysML, UML, Cameo, Python, JavaScript
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
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Digital Design Specialist: Structural Engineering
Irvine or San Diego
$61k-$92k/yr HybridFull Time
4+ YOE4–15 years structural drafting/BIM experience, proficiency in CAD and Revit, strong communication, detail-oriented, able to produce construction documentation; Associate degree in drafting preferred.
CAD, Revit, BIM
1d
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
9+ YOEBachelor's degree in a related technical field and 9+ years of FPGA, ASIC, or SoC digital design experience; HDL, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
ASIC, FPGA, SoC, HDL, RTL
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Principal Electrical Design Engineer
Phoenix or Huntsville or Cypress or Andover or Chantilly or Alpharetta or Torrance or Gulf Breeze
OnsiteFull Time
6+ YOEBS in Electrical/Computer Engineering; 6+ years embedded hardware design; high-speed digital design; lead and mentor engineers; travel; security clearance awareness
Cadence Allegro, Mentor, JAMA, DOORS, JIRA, Confluence, FMEA/DFM/DFT
2mo
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Hardware Design Engineer
Malibu, California, United States
$155k-$198k/yr OnsiteFull Time
BS/MS in Electrical Engineering or Physics; experience from full hardware development cycle; high-speed digital design; CAD tools; strong communication and collaboration
Allegro
6d
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Electronics Design Engineer
Los Angeles, California, United States
$100k-$130k/yr HybridFull Time
2+ YOEBachelor's degree in electrical or computer engineering, 2+ years of multilayer PCB design, digital communication peripherals, power circuitry, test equipment, and U.S. Person status required.
Altium Designer, Xilinx FPGAs, Vivado IDE, MATLAB, Python, C, DMM, oscilloscope, logic analyzer, spectrum analyzer, Ethernet, USB 2.0, I2C, RS232, FCC, CE Mark, MIL-STD-461
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Sr. Manager, Design Assurance Engineering
Pomona or Brea
$152k-$185k/yr OnsiteFull Time
10+ YOE5+ MgmtBachelor's in Engineering, 10+ years in regulated industry, 5+ years leading teams; expertise in design controls, supplier quality, validation, CAPA, audits, and digital quality systems.
eQMS, eDHR, Lean, Six Sigma
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Manager Digital Engineering 2
Woodland Hills, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOESTEM degree with 6–8+ years relevant experience, experience leading technical teams, digital design/verification knowledge (FPGA/SoC/ASIC), PLM experience, ability to obtain/maintain U.S. security clearance, U.S. citizenship required.
FPGA, SoC, ASIC, Product Lifecycle Management (PLM), Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW \u00096 Active Workspace, System Verilog, UVM, Hardware-In-Loop, MATLAB, Simulink, DO-254, RCCAs, BOE, EMV S
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Manager Digital Engineering 2
Los Angeles, California, United States
$161k-$242k/yr OnsiteFull Time
6+ YOEU.S. citizen able to obtain security clearance; STEM bachelor's + 8 years or master's + 6 years; experience leading technical teams in digital design (FPGA/SoC/ASIC); PLM and cost estimating experience; strong communication skills.
PLM, Siemens Teamcenter Enterprise, Teamcenter Unified Architecture (UA), Tc AW – Active Workspace, MATLAB, Simulink, System Verilog, UVM, Hardware-In-Loop
2w
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Electronic Design Engineer, Principal
Morrisville or Long Beach
OnsiteFull Time
10+ YOEBachelor's degree in electrical engineering or equivalent, 10+ years of applicable experience, mixed-signal circuit design, analog and digital controls, power supplies, interfaces, simulation tools, and lab testing experience.
ADS, LTspice, Microwave Office, I2C, CAN, SPI, CPLD, FPGA, RSU
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PCB Design Engineer
Foothill Ranch, California, United States
$115k-$145k/yr OnsiteFull Time
4+ YOE4+ years PCB design experience, proficiency with Altium Designer, multilayer PCB layout, analog/digital circuit knowledge, prototype bring-up, and lab test equipment.
Altium Designer, Draftsman, OutputJob, LTspice, Micro-Cap, Simulink, Gerber, Oscilloscope, Multimeter, Function Generator, Power Supply
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