475 engineer digital design engineering jobs at 197 companies in California
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Digital Design Engineer
San Jose, California, United States
$166k-$229k/yr OnsiteFull Time
Master's degree in electrical, electronics, or computer engineering required. Requires C/C++ or Python, Verilog, VLSI design, signal processing, digital and analog IC design, design automation, and computer architecture knowledge.
C, C++, Python, Verilog
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
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Senior Digital Design Engineer
San Diego, California, United States
$129k-$173k/yr OnsiteFull Time
Independently plans and performs digital design, baseband design, signal integrity analysis, simulation, hardware integration, testing, and platform development. Master's degree accepted in engineering, computer science, or related field.
CAD, PWB
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
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Digital Design Engineer – Senior Engineering Specialist
El Segundo, California, United States
$129k-$250k/yr OnsiteFull Time
12+ YOEBachelor's in electrical engineering, 12+ years experience in space digital/mixed-signal hardware, US citizenship and ability to obtain security clearance, experience with space qualification, radiation testing, WCCA, HyperLynx and PSPICE, strong troubleshooting and communication skills.
HyperLynx, PSPICE, VHDL, Verilog, System Verilog
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering, 12+ years of processor or complex SoC digital design, expert Verilog/SystemVerilog, and expertise in microarchitecture, synthesis, timing, CDC, RDC, and low-power design.
Verilog, SystemVerilog, RISC-V, ARM, MIPS, ARC, ISO 26262, DO-254, EDA
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering; 12+ years in processor, CPU, DSP, or complex SoC digital design; expert Verilog/SystemVerilog and processor microarchitecture expertise.
Verilog, SystemVerilog, EDA
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Senior HSIO Digital Design Engineer
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
3+ YOE3+ years industry experience in digital HSIO or die-to-die interfaces; BS/MS/PhD in Electrical Engineering with specified experience; knowledge of high-speed serial protocols, SI/PI, and digital/analog co-design.
AXI, CHI, CXS.B, CXL, PCIE, UA-Link
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Electrical Engineering Digital Design Lead
Irvine or Los Angeles
OnsiteFull Time
5+ YOETechnical degree or equivalent, minimum 5 years industry experience, advanced 3D design and coordination skills, competency with document management and Microsoft Office, strong understanding of engineering/architectural concepts and standards, excellent communication and organization.
BIM, Microsoft Office
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
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Digital Design Engineer, Air Dominance and Strike
Costa Mesa, California, United States
$146k-$194k/yr OnsiteFull Time
2+ YOEBachelor's degree in electrical or computer engineering, 2+ years of FPGA, ASIC, or digital design experience, VHDL/Verilog proficiency, Linux, Git, Tcl/Python, and eligibility for a U.S. Secret clearance.
VHDL, Verilog, SystemVerilog, Linux, Git, Tcl, Python, AMD (Xilinx), Intel/Altera, Lattice, AMD (Xilinx) Vitis, Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, MIL-STD-1553, DO-254, Jira
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Machine Learning Digital Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent, 8+ years hardware design experience for production silicon, expertise in digital µarchitecture, RTL coding, micro-architecture development, and cross-functional technical communication.
RTL, SoC, ASIC, DSP, microcontrollers
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
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Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
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